1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2015, National Instruments Corp.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Xilinx Zynq Reset controller driver
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Moritz Fischer <moritz.fischer@ettus.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/err.h>
11*4882a593Smuzhiyun #include <linux/io.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
14*4882a593Smuzhiyun #include <linux/of.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include <linux/reset-controller.h>
17*4882a593Smuzhiyun #include <linux/regmap.h>
18*4882a593Smuzhiyun #include <linux/types.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun struct zynq_reset_data {
21*4882a593Smuzhiyun struct regmap *slcr;
22*4882a593Smuzhiyun struct reset_controller_dev rcdev;
23*4882a593Smuzhiyun u32 offset;
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define to_zynq_reset_data(p) \
27*4882a593Smuzhiyun container_of((p), struct zynq_reset_data, rcdev)
28*4882a593Smuzhiyun
zynq_reset_assert(struct reset_controller_dev * rcdev,unsigned long id)29*4882a593Smuzhiyun static int zynq_reset_assert(struct reset_controller_dev *rcdev,
30*4882a593Smuzhiyun unsigned long id)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun struct zynq_reset_data *priv = to_zynq_reset_data(rcdev);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun int bank = id / BITS_PER_LONG;
35*4882a593Smuzhiyun int offset = id % BITS_PER_LONG;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__,
38*4882a593Smuzhiyun bank, offset);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun return regmap_update_bits(priv->slcr,
41*4882a593Smuzhiyun priv->offset + (bank * 4),
42*4882a593Smuzhiyun BIT(offset),
43*4882a593Smuzhiyun BIT(offset));
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
zynq_reset_deassert(struct reset_controller_dev * rcdev,unsigned long id)46*4882a593Smuzhiyun static int zynq_reset_deassert(struct reset_controller_dev *rcdev,
47*4882a593Smuzhiyun unsigned long id)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun struct zynq_reset_data *priv = to_zynq_reset_data(rcdev);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun int bank = id / BITS_PER_LONG;
52*4882a593Smuzhiyun int offset = id % BITS_PER_LONG;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__,
55*4882a593Smuzhiyun bank, offset);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun return regmap_update_bits(priv->slcr,
58*4882a593Smuzhiyun priv->offset + (bank * 4),
59*4882a593Smuzhiyun BIT(offset),
60*4882a593Smuzhiyun ~BIT(offset));
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
zynq_reset_status(struct reset_controller_dev * rcdev,unsigned long id)63*4882a593Smuzhiyun static int zynq_reset_status(struct reset_controller_dev *rcdev,
64*4882a593Smuzhiyun unsigned long id)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun struct zynq_reset_data *priv = to_zynq_reset_data(rcdev);
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun int bank = id / BITS_PER_LONG;
69*4882a593Smuzhiyun int offset = id % BITS_PER_LONG;
70*4882a593Smuzhiyun int ret;
71*4882a593Smuzhiyun u32 reg;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__,
74*4882a593Smuzhiyun bank, offset);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun ret = regmap_read(priv->slcr, priv->offset + (bank * 4), ®);
77*4882a593Smuzhiyun if (ret)
78*4882a593Smuzhiyun return ret;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun return !!(reg & BIT(offset));
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun static const struct reset_control_ops zynq_reset_ops = {
84*4882a593Smuzhiyun .assert = zynq_reset_assert,
85*4882a593Smuzhiyun .deassert = zynq_reset_deassert,
86*4882a593Smuzhiyun .status = zynq_reset_status,
87*4882a593Smuzhiyun };
88*4882a593Smuzhiyun
zynq_reset_probe(struct platform_device * pdev)89*4882a593Smuzhiyun static int zynq_reset_probe(struct platform_device *pdev)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun struct resource *res;
92*4882a593Smuzhiyun struct zynq_reset_data *priv;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
95*4882a593Smuzhiyun if (!priv)
96*4882a593Smuzhiyun return -ENOMEM;
97*4882a593Smuzhiyun platform_set_drvdata(pdev, priv);
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun priv->slcr = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
100*4882a593Smuzhiyun "syscon");
101*4882a593Smuzhiyun if (IS_ERR(priv->slcr)) {
102*4882a593Smuzhiyun dev_err(&pdev->dev, "unable to get zynq-slcr regmap");
103*4882a593Smuzhiyun return PTR_ERR(priv->slcr);
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
107*4882a593Smuzhiyun if (!res) {
108*4882a593Smuzhiyun dev_err(&pdev->dev, "missing IO resource\n");
109*4882a593Smuzhiyun return -ENODEV;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun priv->offset = res->start;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun priv->rcdev.owner = THIS_MODULE;
115*4882a593Smuzhiyun priv->rcdev.nr_resets = resource_size(res) / 4 * BITS_PER_LONG;
116*4882a593Smuzhiyun priv->rcdev.ops = &zynq_reset_ops;
117*4882a593Smuzhiyun priv->rcdev.of_node = pdev->dev.of_node;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun return devm_reset_controller_register(&pdev->dev, &priv->rcdev);
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun static const struct of_device_id zynq_reset_dt_ids[] = {
123*4882a593Smuzhiyun { .compatible = "xlnx,zynq-reset", },
124*4882a593Smuzhiyun { /* sentinel */ },
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun static struct platform_driver zynq_reset_driver = {
128*4882a593Smuzhiyun .probe = zynq_reset_probe,
129*4882a593Smuzhiyun .driver = {
130*4882a593Smuzhiyun .name = KBUILD_MODNAME,
131*4882a593Smuzhiyun .of_match_table = zynq_reset_dt_ids,
132*4882a593Smuzhiyun },
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun builtin_platform_driver(zynq_reset_driver);
135