xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593SmuzhiyunLogicoreIP designed compatible with Xilinx ZYNQ family.
2*4882a593Smuzhiyun-------------------------------------------------------
3*4882a593Smuzhiyun
4*4882a593SmuzhiyunGeneral concept
5*4882a593Smuzhiyun---------------
6*4882a593Smuzhiyun
7*4882a593SmuzhiyunLogicoreIP design to provide the isolation between processing system
8*4882a593Smuzhiyunand programmable logic. Also provides the list of register set to configure
9*4882a593Smuzhiyunthe frequency.
10*4882a593Smuzhiyun
11*4882a593SmuzhiyunRequired properties:
12*4882a593Smuzhiyun- compatible: shall be one of:
13*4882a593Smuzhiyun	"xlnx,vcu"
14*4882a593Smuzhiyun	"xlnx,vcu-logicoreip-1.0"
15*4882a593Smuzhiyun- reg, reg-names: There are two sets of registers need to provide.
16*4882a593Smuzhiyun	1. vcu slcr
17*4882a593Smuzhiyun	2. Logicore
18*4882a593Smuzhiyun	reg-names should contain name for the each register sequence.
19*4882a593Smuzhiyun- clocks: phandle for aclk and pll_ref clocksource
20*4882a593Smuzhiyun- clock-names: The identification string, "aclk", is always required for
21*4882a593Smuzhiyun   the axi clock. "pll_ref" is required for pll.
22*4882a593SmuzhiyunExample:
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun	xlnx_vcu: vcu@a0040000 {
25*4882a593Smuzhiyun		compatible = "xlnx,vcu-logicoreip-1.0";
26*4882a593Smuzhiyun		reg = <0x0 0xa0040000 0x0 0x1000>,
27*4882a593Smuzhiyun			 <0x0 0xa0041000 0x0 0x1000>;
28*4882a593Smuzhiyun		reg-names = "vcu_slcr", "logicore";
29*4882a593Smuzhiyun		clocks = <&si570_1>, <&clkc 71>;
30*4882a593Smuzhiyun		clock-names = "pll_ref", "aclk";
31*4882a593Smuzhiyun	};
32