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Searched refs:dram_clk_cfg (Results 1 – 9 of 9) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c381 clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); in mctl_sys_init()
386 clrsetbits_le32(&ccm->dram_clk_cfg, in mctl_sys_init()
394 clrsetbits_le32(&ccm->dram_clk_cfg, in mctl_sys_init()
401 mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); in mctl_sys_init()
408 setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); in mctl_sys_init()
H A Ddram_sun8i_a83t.c402 clrbits_le32(&ccm->dram_clk_cfg, 0x01<<31); in mctl_sys_init()
406 clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK, in mctl_sys_init()
409 mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); in mctl_sys_init()
H A Ddram_sun8i_a33.c310 clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK, in mctl_sys_init()
313 mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); in mctl_sys_init()
H A Ddram_sun9i.c295 writel((3 << 12) | (1 << 16), &ccm->dram_clk_cfg); in mctl_sys_init()
299 } while (readl(&ccm->dram_clk_cfg) & (1 << 16)); in mctl_sys_init()
300 setbits_le32(&ccm->dram_clk_cfg, (1 << 31)); in mctl_sys_init()
H A Ddram_sun6i.c38 clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK, in mctl_sys_init()
41 mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); in mctl_sys_init()
H A Ddram_sun8i_a23.c225 setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); in mctl_init()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun9i.h62 u32 dram_clk_cfg; /* 0x484 DRAM (controller) clock config */ member
H A Dclock_sun8i_a83t.h64 u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */ member
H A Dclock_sun6i.h67 u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */ member