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Searched refs:aud_1_parents (Results 1 – 6 of 6) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/clk/mediatek/
H A Dclk-mt6797.c272 static const char * const aud_1_parents[] = { variable
365 MUX_GATE(CLK_TOP_MUX_AUD_1, "aud_1_sel", aud_1_parents,
H A Dclk-mt6779.c541 static const char * const aud_1_parents[] = { variable
756 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1, "aud_1_sel", aud_1_parents,
H A Dclk-mt8173.c405 static const char * const aud_1_parents[] __initconst = { variable
579 MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 31),
H A Dclk-mt6765.c274 static const char * const aud_1_parents[] = { variable
422 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents,
H A Dclk-mt8183.c508 static const char * const aud_1_parents[] = { variable
653 aud_1_parents, 0xe0,
H A Dclk-mt2712.c475 static const char * const aud_1_parents[] = { variable
797 aud_1_parents, 0x0a0, 24, 2, 31),