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Searched refs:WREG32_PCIE (Results 1 – 21 of 21) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Dumc_v8_7.c66 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
70 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
79 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
83 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
124 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_query_correctable_error_count()
134 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_query_correctable_error_count()
300 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_err_cnt_init_per_channel()
302 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V8_7_CE_CNT_INIT); in umc_v8_7_err_cnt_init_per_channel()
307 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_err_cnt_init_per_channel()
308 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V8_7_CE_CNT_INIT); in umc_v8_7_err_cnt_init_per_channel()
H A Dumc_v6_1.c55 WREG32_PCIE(rsmu_umc_addr * 4, rsmu_umc_val); in umc_v6_1_enable_umc_index_mode()
70 WREG32_PCIE(rsmu_umc_addr * 4, rsmu_umc_val); in umc_v6_1_disable_umc_index_mode()
123 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
127 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
136 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
140 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
199 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_1_query_correctable_error_count()
209 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_1_query_correctable_error_count()
433 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_1_err_cnt_init_per_channel()
435 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V6_1_CE_CNT_INIT); in umc_v6_1_err_cnt_init_per_channel()
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H A Dcik.c1540 WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, tmp); in cik_pcie_gen3_enable()
1566 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable()
1570 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable()
1617 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable()
1626 WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); in cik_pcie_gen3_enable()
1641 WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); in cik_pcie_gen3_enable()
1672 WREG32_PCIE(ixPCIE_LC_N_FTS_CNTL, data); in cik_program_aspm()
1677 WREG32_PCIE(ixPCIE_LC_CNTL3, data); in cik_program_aspm()
1682 WREG32_PCIE(ixPCIE_P_CNTL, data); in cik_program_aspm()
1695 WREG32_PCIE(ixPCIE_LC_CNTL, data); in cik_program_aspm()
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H A Dnbio_v6_1.c170 WREG32_PCIE(smnCPM_CONTROL, data); in nbio_v6_1_update_medium_grain_clock_gating()
190 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v6_1_update_medium_grain_light_sleep()
253 WREG32_PCIE(smnPCIE_CONFIG_CNTL, data); in nbio_v6_1_init_registers()
259 WREG32_PCIE(smnPCIE_CI_CNTL, data); in nbio_v6_1_init_registers()
H A Dnbio_v7_4.c219 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v7_4_update_medium_grain_light_sleep()
511 WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO, global_sts); in nbio_v7_4_query_ras_error_count()
515 WREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2, in nbio_v7_4_query_ras_error_count()
521 WREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS, central_sts); in nbio_v7_4_query_ras_error_count()
525 WREG32_PCIE(smnIOHC_INTERRUPT_EOI, int_eoi); in nbio_v7_4_query_ras_error_count()
H A Dnbio_v2_3.c229 WREG32_PCIE(smnCPM_CONTROL, data); in nbio_v2_3_update_medium_grain_clock_gating()
249 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v2_3_update_medium_grain_light_sleep()
312 WREG32_PCIE(smnPCIE_CONFIG_CNTL, data); in nbio_v2_3_init_registers()
H A Dnbio_v7_0.c171 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data); in nbio_v7_0_update_medium_grain_clock_gating()
213 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v7_0_update_medium_grain_light_sleep()
H A Dsoc15.c888 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); in soc15_get_pcie_usage()
894 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); in soc15_get_pcie_usage()
903 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); in soc15_get_pcie_usage()
937 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); in vega20_get_pcie_usage()
943 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); in vega20_get_pcie_usage()
952 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); in vega20_get_pcie_usage()
H A Dvi.c1015 WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr); in vi_get_pcie_usage()
1021 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005); in vi_get_pcie_usage()
1030 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002); in vi_get_pcie_usage()
1425 WREG32_PCIE(ixPCIE_CNTL2, data); in vi_update_bif_medium_grain_light_sleep()
H A Dsi.c1483 WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr); in si_get_pcie_usage()
1489 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005); in si_get_pcie_usage()
1498 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002); in si_get_pcie_usage()
2358 WREG32_PCIE(PCIE_P_CNTL, data); in si_program_aspm()
2521 WREG32_PCIE(PCIE_CNTL2, data); in si_program_aspm()
H A Damdgpu_xgmi.c687 WREG32_PCIE(pcs_status_reg, 0xFFFFFFFF); in pcs_clear_status()
688 WREG32_PCIE(pcs_status_reg, 0); in pcs_clear_status()
H A Damdgpu_cgs.c92 return WREG32_PCIE(index, value); in amdgpu_cgs_write_ind_register()
H A Damdgpu.h1075 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) macro
H A Dgmc_v7_0.c880 WREG32_PCIE(ixPCIE_CNTL2, data); in gmc_v7_0_enable_bif_mgls()
H A Damdgpu_debugfs.c425 WREG32_PCIE(*pos, value); in amdgpu_debugfs_regs_pcie_write()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/
H A Dr300.c96 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); in rv370_pcie_gart_tlb_flush()
98 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_tlb_flush()
168 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_enable()
169 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start); in rv370_pcie_gart_enable()
171 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); in rv370_pcie_gart_enable()
172 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); in rv370_pcie_gart_enable()
173 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); in rv370_pcie_gart_enable()
175 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); in rv370_pcie_gart_enable()
177 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); in rv370_pcie_gart_enable()
178 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); in rv370_pcie_gart_enable()
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H A Dsi.c5582 WREG32_PCIE(PCIE_CNTL2, data); in si_enable_bif_mgls()
7299 WREG32_PCIE(PCIE_P_CNTL, data); in si_program_aspm()
7462 WREG32_PCIE(PCIE_CNTL2, data); in si_program_aspm()
H A Drv6xx_dpm.c135 WREG32_PCIE(PCIE_P_CNTL, tmp); in rv6xx_enable_pll_sleep_in_l1()
H A Drv770_dpm.c126 WREG32_PCIE(PCIE_P_CNTL, tmp); in rv770_enable_pll_sleep_in_l1()
H A Dradeon.h2531 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dsmu_v11_0.c174 WREG32_PCIE(addr_start, src[i]); in smu_v11_0_load_microcode()
178 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), in smu_v11_0_load_microcode()
180 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), in smu_v11_0_load_microcode()