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Searched refs:SCLK_NANDC_DIV50 (Results 1 – 7 of 7) sorted by relevance

/OK3568_Linux_fs/u-boot/include/dt-bindings/clock/
H A Drk3308-cru.h57 #define SCLK_NANDC_DIV50 44 macro
H A Dpx30-cru.h94 #define SCLK_NANDC_DIV50 79 macro
/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dpx30-cru.h81 #define SCLK_NANDC_DIV50 79 macro
H A Drk3308-cru.h48 #define SCLK_NANDC_DIV50 44 macro
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-rk3308.c484 COMPOSITE(SCLK_NANDC_DIV50, "clk_nandc_div50", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
H A Dclk-px30.c461 COMPOSITE(SCLK_NANDC_DIV50, "clk_nandc_div50", mux_gpll_cpll_npll_p, 0,
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Dpx30.dtsi1440 assigned-clock-parents = <&cru SCLK_NANDC_DIV50>;