Searched refs:PLL_POSTDIV2_SHIFT (Results 1 – 12 of 12) sorted by relevance
95 PLL_POSTDIV2_SHIFT = 6, enumerator96 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
148 PLL_POSTDIV2_SHIFT = 6, enumerator149 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
119 PLL_POSTDIV2_SHIFT = 6, enumerator120 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
31 #define PLL_POSTDIV2_SHIFT 6 macro81 postdiv2 = (con1 & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in clk_regmap_pll_recalc_rate()
34 #define PLL_POSTDIV2_SHIFT 6 macro
93 postdiv2 = (con1 & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in rk628_cru_clk_get_rate_pll()
94 postdiv2 = (con1 & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in rk628_cru_clk_get_rate_pll()
89 (div->postdiv2 << PLL_POSTDIV2_SHIFT | in rkclk_set_pll()233 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in rkclk_pll_get_rate()
101 PLL_POSTDIV2_SHIFT = 12, enumerator102 PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT,357 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in rkclk_pll_get_rate()396 (div->postdiv2 << PLL_POSTDIV2_SHIFT) | in rkclk_set_pll()
253 (rate->postdiv2 << PLL_POSTDIV2_SHIFT | in rkclk_set_pll()288 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in rkclk_pll_get_rate()
343 (dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT | in rkdclk_init()