Searched refs:PLL_POSTDIV1_SHIFT (Results 1 – 12 of 12) sorted by relevance
82 PLL_POSTDIV1_SHIFT = 12, enumerator83 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
134 PLL_POSTDIV1_SHIFT = 12, enumerator135 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
103 PLL_POSTDIV1_SHIFT = 12, enumerator104 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
24 #define PLL_POSTDIV1_SHIFT 12 macro78 postdiv1 = (con0 & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in clk_regmap_pll_recalc_rate()
21 #define PLL_POSTDIV1_SHIFT 12 macro
90 postdiv1 = (con0 & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rk628_cru_clk_get_rate_pll()
91 postdiv1 = (con0 & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rk628_cru_clk_get_rate_pll()
87 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()230 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rkclk_pll_get_rate()
103 PLL_POSTDIV1_SHIFT = 8, enumerator104 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT,356 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rkclk_pll_get_rate()397 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | in rkclk_set_pll()
251 (rate->postdiv1 << PLL_POSTDIV1_SHIFT) | rate->fbdiv); in rkclk_set_pll()285 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rkclk_pll_get_rate()
340 (dpll_init_cfg.postdiv1 << PLL_POSTDIV1_SHIFT) | in rkdclk_init()