Searched +full:sun9i +full:- +full:a80 +full:- +full:usb +full:- +full:phy +full:- +full:clk (Results 1 – 9 of 9) sorted by relevance
2 * Copyright 2014 Chen-Yu Tsai4 * Chen-Yu Tsai <wens@csie.org>6 * This file is dual-licensed: you can use it either under the terms47 #include <dt-bindings/interrupt-controller/arm-gic.h>49 #include <dt-bindings/pinctrl/sun4i-a10.h>52 interrupt-parent = <&gic>;55 #address-cells = <1>;56 #size-cells = <0>;59 compatible = "arm,cortex-a7";65 compatible = "arm,cortex-a7";[all …]
2 * Copyright 2014 Chen-Yu Tsai4 * Chen-Yu Tsai <wens@csie.org>6 * This file is dual-licensed: you can use it either under the terms45 #include <dt-bindings/interrupt-controller/arm-gic.h>47 #include <dt-bindings/clock/sun9i-a80-ccu.h>48 #include <dt-bindings/clock/sun9i-a80-de.h>49 #include <dt-bindings/clock/sun9i-a80-usb.h>50 #include <dt-bindings/reset/sun9i-a80-ccu.h>51 #include <dt-bindings/reset/sun9i-a80-de.h>52 #include <dt-bindings/reset/sun9i-a80-usb.h>[all …]
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-usb-phy-clk.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Allwinner A80 USB PHY Clock Device Tree Bindings10 - Chen-Yu Tsai <wens@csie.org>11 - Maxime Ripard <mripard@kernel.org>16 "#clock-cells":22 "#reset-cells":26 const: allwinner,sun9i-a80-usb-phy-clk[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.6 #include <linux/clk.h>7 #include <linux/clk-provider.h>15 #include "ccu-sun9i-a80-usb.h"25 static SUNXI_CCU_GATE_DATA(bus_hci0_clk, "bus-hci0", clk_parent_bus, 0x0, BIT(1), 0);26 static SUNXI_CCU_GATE_DATA(usb_ohci0_clk, "usb-ohci0", clk_parent_hosc, 0x0, BIT(2), 0);27 static SUNXI_CCU_GATE_DATA(bus_hci1_clk, "bus-hci1", clk_parent_bus, 0x0, BIT(3), 0);28 static SUNXI_CCU_GATE_DATA(bus_hci2_clk, "bus-hci2", clk_parent_bus, 0x0, BIT(5), 0);29 static SUNXI_CCU_GATE_DATA(usb_ohci2_clk, "usb-ohci2", clk_parent_hosc, 0x0, BIT(6), 0);[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later3 * Allwinner sun9i USB phy driver5 * Copyright (C) 2014-2015 Chen-Yu Tsai <wens@csie.org>7 * Based on phy-sun4i-usb.c from14 #include <linux/clk.h>18 #include <linux/phy/phy.h>19 #include <linux/usb/of.h>36 struct phy *phy; member39 struct clk *clk; member40 struct clk *hsic_clk;[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later3 * Copyright 2013-2015 Emilio López8 #include <linux/clk.h>9 #include <linux/clk-provider.h>13 #include <linux/reset-controller.h>19 * sunxi_usb_reset... - reset bits in usb clk registers handling25 struct clk *clk; member38 clk_prepare_enable(data->clk); in sunxi_usb_reset_assert()39 spin_lock_irqsave(data->lock, flags); in sunxi_usb_reset_assert()41 reg = readl(data->reg); in sunxi_usb_reset_assert()[all …]
9 * SPDX-License-Identifier: GPL-2.0+17 #include <usb.h>31 int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */32 int usb_gate_mask; /* Mask of usb_clk_cfg clk gate bits for this hcd */33 int phy_index; /* Index of the usb-phy attached to this hcd */43 priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; in ohci_usb_probe()44 if (IS_ERR(priv->ccm)) in ohci_usb_probe()45 return PTR_ERR(priv->ccm); in ohci_usb_probe()47 bus_priv->companion = true; in ohci_usb_probe()53 priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0; in ohci_usb_probe()[all …]
10 * SPDX-License-Identifier: GPL-2.0+31 int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */32 int phy_index; /* Index of the usb-phy attached to this hcd */43 priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; in ehci_usb_probe()44 if (IS_ERR(priv->ccm)) in ehci_usb_probe()45 return PTR_ERR(priv->ccm); in ehci_usb_probe()51 priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0; in ehci_usb_probe()55 priv->phy_index = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST; in ehci_usb_probe()56 priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST; in ehci_usb_probe()57 extra_ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST; in ehci_usb_probe()[all …]
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