1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/clk.h>
7*4882a593Smuzhiyun #include <linux/clk-provider.h>
8*4882a593Smuzhiyun #include <linux/of_address.h>
9*4882a593Smuzhiyun #include <linux/platform_device.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include "ccu_common.h"
12*4882a593Smuzhiyun #include "ccu_gate.h"
13*4882a593Smuzhiyun #include "ccu_reset.h"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include "ccu-sun9i-a80-usb.h"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun static const struct clk_parent_data clk_parent_hosc[] = {
18*4882a593Smuzhiyun { .fw_name = "hosc" },
19*4882a593Smuzhiyun };
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun static const struct clk_parent_data clk_parent_bus[] = {
22*4882a593Smuzhiyun { .fw_name = "bus" },
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun static SUNXI_CCU_GATE_DATA(bus_hci0_clk, "bus-hci0", clk_parent_bus, 0x0, BIT(1), 0);
26*4882a593Smuzhiyun static SUNXI_CCU_GATE_DATA(usb_ohci0_clk, "usb-ohci0", clk_parent_hosc, 0x0, BIT(2), 0);
27*4882a593Smuzhiyun static SUNXI_CCU_GATE_DATA(bus_hci1_clk, "bus-hci1", clk_parent_bus, 0x0, BIT(3), 0);
28*4882a593Smuzhiyun static SUNXI_CCU_GATE_DATA(bus_hci2_clk, "bus-hci2", clk_parent_bus, 0x0, BIT(5), 0);
29*4882a593Smuzhiyun static SUNXI_CCU_GATE_DATA(usb_ohci2_clk, "usb-ohci2", clk_parent_hosc, 0x0, BIT(6), 0);
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun static SUNXI_CCU_GATE_DATA(usb0_phy_clk, "usb0-phy", clk_parent_hosc, 0x4, BIT(1), 0);
32*4882a593Smuzhiyun static SUNXI_CCU_GATE_DATA(usb1_hsic_clk, "usb1-hsic", clk_parent_hosc, 0x4, BIT(2), 0);
33*4882a593Smuzhiyun static SUNXI_CCU_GATE_DATA(usb1_phy_clk, "usb1-phy", clk_parent_hosc, 0x4, BIT(3), 0);
34*4882a593Smuzhiyun static SUNXI_CCU_GATE_DATA(usb2_hsic_clk, "usb2-hsic", clk_parent_hosc, 0x4, BIT(4), 0);
35*4882a593Smuzhiyun static SUNXI_CCU_GATE_DATA(usb2_phy_clk, "usb2-phy", clk_parent_hosc, 0x4, BIT(5), 0);
36*4882a593Smuzhiyun static SUNXI_CCU_GATE_DATA(usb_hsic_clk, "usb-hsic", clk_parent_hosc, 0x4, BIT(10), 0);
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun static struct ccu_common *sun9i_a80_usb_clks[] = {
39*4882a593Smuzhiyun &bus_hci0_clk.common,
40*4882a593Smuzhiyun &usb_ohci0_clk.common,
41*4882a593Smuzhiyun &bus_hci1_clk.common,
42*4882a593Smuzhiyun &bus_hci2_clk.common,
43*4882a593Smuzhiyun &usb_ohci2_clk.common,
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun &usb0_phy_clk.common,
46*4882a593Smuzhiyun &usb1_hsic_clk.common,
47*4882a593Smuzhiyun &usb1_phy_clk.common,
48*4882a593Smuzhiyun &usb2_hsic_clk.common,
49*4882a593Smuzhiyun &usb2_phy_clk.common,
50*4882a593Smuzhiyun &usb_hsic_clk.common,
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun static struct clk_hw_onecell_data sun9i_a80_usb_hw_clks = {
54*4882a593Smuzhiyun .hws = {
55*4882a593Smuzhiyun [CLK_BUS_HCI0] = &bus_hci0_clk.common.hw,
56*4882a593Smuzhiyun [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
57*4882a593Smuzhiyun [CLK_BUS_HCI1] = &bus_hci1_clk.common.hw,
58*4882a593Smuzhiyun [CLK_BUS_HCI2] = &bus_hci2_clk.common.hw,
59*4882a593Smuzhiyun [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun [CLK_USB0_PHY] = &usb0_phy_clk.common.hw,
62*4882a593Smuzhiyun [CLK_USB1_HSIC] = &usb1_hsic_clk.common.hw,
63*4882a593Smuzhiyun [CLK_USB1_PHY] = &usb1_phy_clk.common.hw,
64*4882a593Smuzhiyun [CLK_USB2_HSIC] = &usb2_hsic_clk.common.hw,
65*4882a593Smuzhiyun [CLK_USB2_PHY] = &usb2_phy_clk.common.hw,
66*4882a593Smuzhiyun [CLK_USB_HSIC] = &usb_hsic_clk.common.hw,
67*4882a593Smuzhiyun },
68*4882a593Smuzhiyun .num = CLK_NUMBER,
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun static struct ccu_reset_map sun9i_a80_usb_resets[] = {
72*4882a593Smuzhiyun [RST_USB0_HCI] = { 0x0, BIT(17) },
73*4882a593Smuzhiyun [RST_USB1_HCI] = { 0x0, BIT(18) },
74*4882a593Smuzhiyun [RST_USB2_HCI] = { 0x0, BIT(19) },
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun [RST_USB0_PHY] = { 0x4, BIT(17) },
77*4882a593Smuzhiyun [RST_USB1_HSIC] = { 0x4, BIT(18) },
78*4882a593Smuzhiyun [RST_USB1_PHY] = { 0x4, BIT(19) },
79*4882a593Smuzhiyun [RST_USB2_HSIC] = { 0x4, BIT(20) },
80*4882a593Smuzhiyun [RST_USB2_PHY] = { 0x4, BIT(21) },
81*4882a593Smuzhiyun };
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun static const struct sunxi_ccu_desc sun9i_a80_usb_clk_desc = {
84*4882a593Smuzhiyun .ccu_clks = sun9i_a80_usb_clks,
85*4882a593Smuzhiyun .num_ccu_clks = ARRAY_SIZE(sun9i_a80_usb_clks),
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun .hw_clks = &sun9i_a80_usb_hw_clks,
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun .resets = sun9i_a80_usb_resets,
90*4882a593Smuzhiyun .num_resets = ARRAY_SIZE(sun9i_a80_usb_resets),
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun
sun9i_a80_usb_clk_probe(struct platform_device * pdev)93*4882a593Smuzhiyun static int sun9i_a80_usb_clk_probe(struct platform_device *pdev)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun struct resource *res;
96*4882a593Smuzhiyun struct clk *bus_clk;
97*4882a593Smuzhiyun void __iomem *reg;
98*4882a593Smuzhiyun int ret;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
101*4882a593Smuzhiyun reg = devm_ioremap_resource(&pdev->dev, res);
102*4882a593Smuzhiyun if (IS_ERR(reg))
103*4882a593Smuzhiyun return PTR_ERR(reg);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun bus_clk = devm_clk_get(&pdev->dev, "bus");
106*4882a593Smuzhiyun if (IS_ERR(bus_clk)) {
107*4882a593Smuzhiyun ret = PTR_ERR(bus_clk);
108*4882a593Smuzhiyun if (ret != -EPROBE_DEFER)
109*4882a593Smuzhiyun dev_err(&pdev->dev, "Couldn't get bus clk: %d\n", ret);
110*4882a593Smuzhiyun return ret;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /* The bus clock needs to be enabled for us to access the registers */
114*4882a593Smuzhiyun ret = clk_prepare_enable(bus_clk);
115*4882a593Smuzhiyun if (ret) {
116*4882a593Smuzhiyun dev_err(&pdev->dev, "Couldn't enable bus clk: %d\n", ret);
117*4882a593Smuzhiyun return ret;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun ret = sunxi_ccu_probe(pdev->dev.of_node, reg,
121*4882a593Smuzhiyun &sun9i_a80_usb_clk_desc);
122*4882a593Smuzhiyun if (ret)
123*4882a593Smuzhiyun goto err_disable_clk;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun return 0;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun err_disable_clk:
128*4882a593Smuzhiyun clk_disable_unprepare(bus_clk);
129*4882a593Smuzhiyun return ret;
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun static const struct of_device_id sun9i_a80_usb_clk_ids[] = {
133*4882a593Smuzhiyun { .compatible = "allwinner,sun9i-a80-usb-clks" },
134*4882a593Smuzhiyun { }
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun static struct platform_driver sun9i_a80_usb_clk_driver = {
138*4882a593Smuzhiyun .probe = sun9i_a80_usb_clk_probe,
139*4882a593Smuzhiyun .driver = {
140*4882a593Smuzhiyun .name = "sun9i-a80-usb-clks",
141*4882a593Smuzhiyun .of_match_table = sun9i_a80_usb_clk_ids,
142*4882a593Smuzhiyun },
143*4882a593Smuzhiyun };
144*4882a593Smuzhiyun builtin_platform_driver(sun9i_a80_usb_clk_driver);
145