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/OK3568_Linux_fs/kernel/Documentation/networking/dsa/
H A Dbcm_sf2.rst5 Broadcom's Starfighter 2 Ethernet switch hardware block is commonly found and
8 - xDSL gateways such as BCM63138
9 - streaming/multimedia Set Top Box such as BCM7445
10 - Cable Modem/residential gateways such as BCM7145/BCM3390
12 The switch is typically deployed in a configuration involving between 5 to 13
13 ports, offering a range of built-in and customizable interfaces:
15 - single integrated Gigabit PHY
16 - quad integrated Gigabit PHY
17 - quad external Gigabit PHY w/ MDIO multiplexer
18 - integrated MoCA PHY
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/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc11 ---------
12 The LS1043A integrated multicore processor combines four ARM Cortex-A53
18 - Four 64-bit ARM Cortex-A53 CPUs
19 - 1 MB unified L2 Cache
20 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
22 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
24 - Packet parsing, classification, and distribution (FMan)
25 - Queue management for scheduling, packet sequencing, and congestion
27 - Hardware buffer management for buffer allocation and de-allocation (BMan)
28 - Cryptography acceleration (SEC)
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/dsa/
H A Db53.txt6 - compatible: For external switch chips, compatible string must be exactly one
18 "brcm,bcm11360-srab" and the mandatory "brcm,cygnus-srab" string
20 For the BCM5310x SoCs with an integrated switch, must be one of:
21 "brcm,bcm53010-srab"
22 "brcm,bcm53011-srab"
23 "brcm,bcm53012-srab"
24 "brcm,bcm53018-srab"
25 "brcm,bcm53019-srab" and the mandatory "brcm,bcm5301x-srab" string
27 For the BCM5831X/BCM1140x SoCs with an integrated switch, must be one of:
28 "brcm,bcm11404-srab"
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H A Dvitesse,vsc73xx.txt9 Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
10 Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
11 Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
12 Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
16 If SPI interface is used, the device tree node is an SPI device so it must
17 reside inside a SPI bus device tree node, see spi/spi-bus.txt
19 When the chip is connected to a parallel memory bus and work in memory-mapped
20 I/O mode, a platform device is used to represent the vsc73xx. In this case it
25 - compatible: must be exactly one of:
30 - gpio-controller: indicates that this switch is also a GPIO controller,
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H A Dmt7530.txt6 - compatible: may be compatible = "mediatek,mt7530"
9 - #address-cells: Must be 1.
10 - #size-cells: Must be 0.
11 - mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
12 on multi-chip module belong to MT7623A has or the remotely standalone
15 If compatible mediatek,mt7530 is set then the following properties are required
17 - core-supply: Phandle to the regulator node necessary for the core power.
18 - io-supply: Phandle to the regulator node necessary for the I/O power.
19 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
22 If the property mediatek,mcm isn't defined, following property is required
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H A Dqca8k.txt5 - compatible: should be one of:
9 - #size-cells: must be 0
10 - #address-cells: must be 1
14 - reset-gpios: GPIO to be used to reset the whole device
18 The integrated switch subnode should be specified according to the binding
19 described in dsa/dsa.txt. If the QCA8K switch is connect to a SoC's external
20 mdio-bus each subnode describing a port needs to have a valid phandle
21 referencing the internal PHY it is connected to. This is because there's no
22 N:N mapping of port and PHY id.
24 Don't use mixed external and internal mdio-bus configurations, as this is
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/
H A Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet PHY Generic Binding
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
16 # case, the node name is the one we want to match on, while the
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H A Dsnps,dwc-qos-ethernet.txt3 This binding is deprecated, but it continues to be supported, but new
13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
17 Represents the IP core when integrated into the NVIDIA Tegra186 SoC.
18 - "snps,dwc-qos-ethernet-4.10"
19 This combination is deprecated. It should be treated as equivalent to
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
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H A Dallwinner,sun8i-a83t-emac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - const: allwinner,sun8i-a83t-emac
17 - const: allwinner,sun8i-h3-emac
18 - const: allwinner,sun8i-r40-emac
19 - const: allwinner,sun8i-v3s-emac
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H A Dbrcm,unimac-mdio.txt4 - compatible: should one from "brcm,genet-mdio-v1", "brcm,genet-mdio-v2",
5 "brcm,genet-mdio-v3", "brcm,genet-mdio-v4", "brcm,genet-mdio-v5" or
6 "brcm,unimac-mdio"
7 - reg: address and length of the register set for the device, first one is the
8 base register, and the second one is optional and for indirect accesses to
9 larger than 16-bits MDIO transactions
10 - reg-names: name(s) of the register must be "mdio" and optional "mdio_indir_rw"
11 - #size-cells: must be 1
12 - #address-cells: must be 0
15 - interrupts: must be one if the interrupt is shared with the Ethernet MAC or
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H A Dcortina,gemini-ethernet.txt4 This ethernet controller is found in the Gemini SoC family:
9 - compatible: must be "cortina,gemini-ethernet"
10 - reg: must contain the global registers and the V-bit and A-bit
12 - syscon: a phandle to the system controller
13 - #address-cells: must be specified, must be <1>
14 - #size-cells: must be specified, must be <1>
15 - ranges: should be state like this giving a 1:1 address translation
23 - port0: contains the resources for ethernet port 0
24 - port1: contains the resources for ethernet port 1
27 - compatible: must be "cortina,gemini-ethernet-port"
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H A Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: TI DP83869 ethernet PHY
11 - $ref: "ethernet-phy.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
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/OK3568_Linux_fs/u-boot/drivers/usb/gadget/
H A DKconfig6 # NOTE: Gadget support ** DOES NOT ** depend on host-side CONFIG_USB !!
8 # - Host systems (like PCs) need CONFIG_USB (with "A" jacks).
9 # - Peripherals (like PDAs) need CONFIG_USB_GADGET (with "B" jacks).
10 # - Some systems have both kinds of controllers.
12 # With help from a special transceiver and a "Mini-AB" jack, systems with
13 # both kinds of controller can also support "USB On-the-Go" (CONFIG_USB_OTG).
19 USB is a master/slave protocol, organized with one master
21 The USB hardware is asymmetric, which makes it easier to set up:
22 you can't connect a "to-the-host" connector to a peripheral.
24 U-Boot can run in the host, or in the peripheral. In both cases
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/OK3568_Linux_fs/kernel/drivers/net/phy/
H A Dintel-xway.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
9 #include <linux/phy.h>
17 #define XWAY_MDIO_LED_LED3_EN BIT(11) /* Enable the integrated function of LED3 */
18 #define XWAY_MDIO_LED_LED2_EN BIT(10) /* Enable the integrated function of LED2 */
19 #define XWAY_MDIO_LED_LED1_EN BIT(9) /* Enable the integrated function of LED1 */
20 #define XWAY_MDIO_LED_LED0_EN BIT(8) /* Enable the integrated function of LED0 */
27 #define XWAY_MDIO_INIT_WOL BIT(15) /* Wake-On-LAN */
31 #define XWAY_MDIO_INIT_ANE BIT(11) /* Auto-Neg error */
32 #define XWAY_MDIO_INIT_ANC BIT(10) /* Auto-Neg complete */
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # PHY Layer Configuration
12 PHYlink models the link between the PHY and MAC, allowing fixed
17 tristate "PHY Device support and infrastructure"
22 Ethernet controllers are usually attached to PHY
24 managing PHY devices.
35 Adds support for a set of LED trigger events per-PHY. Link
38 supported by the PHY and also a one common "link" trigger as a
39 logical-or of all the link speed ones.
41 <mii bus id>:<phy>:<speed>
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/wiznet/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
26 W5100 is a single chip with integrated 10/100 Ethernet MAC,
27 PHY and hardware TCP/IP stack, but this driver is limited to
28 the MAC and PHY functions only, onchip TCP/IP is unused.
39 W5300 is a single chip with integrated 10/100 Ethernet MAC,
40 PHY and hardware TCP/IP stack, but this driver is limited to
41 the MAC and PHY functions only, onchip TCP/IP is unused.
55 after mapping to Memory-Mapped I/O space.
62 which are directly mapped to Memory-Mapped I/O space.
67 If interface mode is unknown in compile time, it can be selected
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/OK3568_Linux_fs/u-boot/board/freescale/t1040qds/
H A DREADME2 --------
3 The T1040QDS is a Freescale reference board that hosts the T1040 SoC
7 ------------------
8 The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
9 processor cores with high-performance data path acceleration architecture
14 - Four e5500 cores, each with a private 256 KB L2 cache
15 - 256 KB shared L3 CoreNet platform cache (CPC)
16 - Interconnect CoreNet platform
17 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
19 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
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/OK3568_Linux_fs/u-boot/doc/device-tree-bindings/net/
H A Dsnps,dwc-qos-ethernet.txt10 - compatible: One of:
11 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
12 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
13 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
14 Represents the IP core when integrated into the NVIDIA Tegra186 SoC.
15 - "snps,dwc-qos-ethernet-4.10"
16 This combination is deprecated. It should be treated as equivalent to
17 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
19 - reg: Address and length of the register set for the device
20 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/bsc9132qds/
H A DREADME2 --------
3 The BSC9132 is a highly integrated device that targets the evolving
4 Microcell, Picocell, and Enterprise-Femto base station market subsegments.
7 core technologies with MAPLE-B2P baseband acceleration processing elements
8 to address the need for a high performance, low cost, integrated solution
15 - Power Architecture subsystem including two e500 processors with
16 512-Kbyte shared L2 cache
17 - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
19 - 32 Kbyte of shared M3 memory
20 - The Multi Accelerator Platform Engine for Pico BaseStation Baseband
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/OK3568_Linux_fs/u-boot/board/freescale/ls1021atwr/
H A DREADME2 --------
3 The LS1021ATWR is a Freescale reference board that hosts the LS1021A SoC.
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/ls1021aqds/
H A DREADME2 --------
3 The LS1021AQDS is a Freescale reference board that hosts the LS1021A SoC.
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
[all …]
/OK3568_Linux_fs/kernel/drivers/scsi/mpt3sas/
H A Dmpt3sas_base.h2 * This is the Fusion MPT base driver providing common API layer interface
5 * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.h
6 * Copyright (C) 2012-2014 LSI Corporation
7 * Copyright (C) 2013-2014 Avago Technologies
8 * (mailto: MPT-FusionLinux.pdl@avagotech.com)
10 * This program is free software; you can redistribute it and/or
15 * This program is distributed in the hope that it will be useful,
21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Drk3228-evb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
9 compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
16 vcc_phy: vcc-phy-regulator {
17 compatible = "regulator-fixed";
18 enable-active-high;
19 regulator-name = "vcc_phy";
20 regulator-min-microvolt = <1800000>;
21 regulator-max-microvolt = <1800000>;
22 regulator-always-on;
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/bsc9131rdb/
H A DREADME2 --------
3 - BSC9131 is integrated device that targets Femto base station market.
5 technologies with MAPLE-B2F baseband acceleration processing elements.
6 - It's MAPLE disabled personality is called 9231.
9 . Power Architecture subsystem including a e500 processor with 256-Kbyte shared
11 . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
13 Processing (MAPLE-B2F)
14 . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
20 . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
21 ECC, up to 400-MHz clock/800 MHz data rate
[all …]
/OK3568_Linux_fs/kernel/drivers/net/mdio/
H A Dmdio-bcm-unimac.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2014-2017 Broadcom
16 #include <linux/phy.h>
17 #include <linux/platform_data/mdio-bcm-unimac.h>
50 * peripheral registers for CPU-native byte order. in unimac_mdio_readl()
53 return __raw_readl(priv->base + offset); in unimac_mdio_readl()
55 return readl_relaxed(priv->base + offset); in unimac_mdio_readl()
62 __raw_writel(val, priv->base + offset); in unimac_mdio_writel()
64 writel_relaxed(val, priv->base + offset); in unimac_mdio_writel()
91 } while (--timeout); in unimac_mdio_poll()
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