1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun/dts-v1/; 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun#include "rk322x.dtsi" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun model = "Rockchip RK3228 Evaluation board"; 9*4882a593Smuzhiyun compatible = "rockchip,rk3228-evb", "rockchip,rk3228"; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun memory@60000000 { 12*4882a593Smuzhiyun device_type = "memory"; 13*4882a593Smuzhiyun reg = <0x60000000 0x40000000>; 14*4882a593Smuzhiyun }; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun vcc_phy: vcc-phy-regulator { 17*4882a593Smuzhiyun compatible = "regulator-fixed"; 18*4882a593Smuzhiyun enable-active-high; 19*4882a593Smuzhiyun regulator-name = "vcc_phy"; 20*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 21*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 22*4882a593Smuzhiyun regulator-always-on; 23*4882a593Smuzhiyun regulator-boot-on; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun}; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun&emmc { 28*4882a593Smuzhiyun cap-mmc-highspeed; 29*4882a593Smuzhiyun mmc-ddr-1_8v; 30*4882a593Smuzhiyun disable-wp; 31*4882a593Smuzhiyun non-removable; 32*4882a593Smuzhiyun status = "okay"; 33*4882a593Smuzhiyun}; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun&gmac { 36*4882a593Smuzhiyun assigned-clocks = <&cru SCLK_MAC_SRC>; 37*4882a593Smuzhiyun assigned-clock-rates = <50000000>; 38*4882a593Smuzhiyun clock_in_out = "output"; 39*4882a593Smuzhiyun phy-supply = <&vcc_phy>; 40*4882a593Smuzhiyun phy-mode = "rmii"; 41*4882a593Smuzhiyun phy-handle = <&phy>; 42*4882a593Smuzhiyun status = "okay"; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun mdio { 45*4882a593Smuzhiyun compatible = "snps,dwmac-mdio"; 46*4882a593Smuzhiyun #address-cells = <1>; 47*4882a593Smuzhiyun #size-cells = <0>; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun phy: ethernet-phy@0 { 50*4882a593Smuzhiyun compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; 51*4882a593Smuzhiyun reg = <0>; 52*4882a593Smuzhiyun clocks = <&cru SCLK_MAC_PHY>; 53*4882a593Smuzhiyun resets = <&cru SRST_MACPHY>; 54*4882a593Smuzhiyun phy-is-integrated; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun}; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun&tsadc { 60*4882a593Smuzhiyun status = "okay"; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 63*4882a593Smuzhiyun rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ 64*4882a593Smuzhiyun}; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun&uart2 { 67*4882a593Smuzhiyun status = "okay"; 68*4882a593Smuzhiyun}; 69