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/OK3568_Linux_fs/external/security/rk_tee_user/v2/host/xtest/
H A Dregression_5000.c83 static void CloseSession_null(struct xtest_session *cs) in CloseSession_null() argument
85 Do_ADBG_BeginSubCase(cs->c, "CloseSession_null"); in CloseSession_null()
90 Do_ADBG_EndSubCase(cs->c, "CloseSession_null"); in CloseSession_null()
93 static void Allocate_In(struct xtest_session *cs) in Allocate_In() argument
95 Do_ADBG_BeginSubCase(cs->c, "Allocate_In"); in Allocate_In()
100 if (!ADBG_EXPECT(cs->c, TEEC_SUCCESS, in Allocate_In()
101 TEEC_InitializeContext(xtest_tee_name, &cs->context))) in Allocate_In()
104 if (!ADBG_EXPECT_TEEC_SUCCESS(cs->c, in Allocate_In()
105 AllocateSharedMemory(&cs->context, &shm, size, in Allocate_In()
111 TEEC_FinalizeContext(&cs->context); in Allocate_In()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gt/
H A Dgen6_engine_cs.c31 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
59 u32 *cs; in gen6_emit_post_sync_nonzero_flush() local
61 cs = intel_ring_begin(rq, 6); in gen6_emit_post_sync_nonzero_flush()
62 if (IS_ERR(cs)) in gen6_emit_post_sync_nonzero_flush()
63 return PTR_ERR(cs); in gen6_emit_post_sync_nonzero_flush()
65 *cs++ = GFX_OP_PIPE_CONTROL(5); in gen6_emit_post_sync_nonzero_flush()
66 *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; in gen6_emit_post_sync_nonzero_flush()
67 *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; in gen6_emit_post_sync_nonzero_flush()
68 *cs++ = 0; /* low dword */ in gen6_emit_post_sync_nonzero_flush()
69 *cs++ = 0; /* high dword */ in gen6_emit_post_sync_nonzero_flush()
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H A Dgen2_engine_cs.c17 u32 cmd, *cs; in gen2_emit_flush() local
23 cs = intel_ring_begin(rq, 2 + 4 * num_store_dw); in gen2_emit_flush()
24 if (IS_ERR(cs)) in gen2_emit_flush()
25 return PTR_ERR(cs); in gen2_emit_flush()
27 *cs++ = cmd; in gen2_emit_flush()
29 *cs++ = MI_STORE_DWORD_INDEX; in gen2_emit_flush()
30 *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32); in gen2_emit_flush()
31 *cs++ = 0; in gen2_emit_flush()
32 *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH; in gen2_emit_flush()
34 *cs++ = cmd; in gen2_emit_flush()
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H A Dgen7_renderclear.c11 #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS)) argument
101 static u32 batch_offset(const struct batch_chunk *bc, u32 *cs) in batch_offset() argument
103 return (cs - bc->start) * sizeof(*bc->start) + bc->offset; in batch_offset()
147 u32 *cs = batch_alloc_items(state, 32, 8); in gen7_fill_surface_state() local
148 u32 offset = batch_offset(state, cs); in gen7_fill_surface_state()
154 *cs++ = SURFACE_2D << 29 | in gen7_fill_surface_state()
158 *cs++ = batch_addr(state) + dst_offset; in gen7_fill_surface_state()
160 *cs++ = ((surface_h / 4 - 1) << 16) | (surface_w / 4 - 1); in gen7_fill_surface_state()
161 *cs++ = surface_w; in gen7_fill_surface_state()
162 *cs++ = 0; in gen7_fill_surface_state()
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/OK3568_Linux_fs/kernel/kernel/time/
H A Dclocksource.c119 static void __clocksource_change_rating(struct clocksource *cs, int rating);
152 static void __clocksource_unstable(struct clocksource *cs) in __clocksource_unstable() argument
154 cs->flags &= ~(CLOCK_SOURCE_VALID_FOR_HRES | CLOCK_SOURCE_WATCHDOG); in __clocksource_unstable()
155 cs->flags |= CLOCK_SOURCE_UNSTABLE; in __clocksource_unstable()
161 if (list_empty(&cs->list)) { in __clocksource_unstable()
162 cs->rating = 0; in __clocksource_unstable()
166 if (cs->mark_unstable) in __clocksource_unstable()
167 cs->mark_unstable(cs); in __clocksource_unstable()
176 * @cs: clocksource to be marked unstable
181 void clocksource_mark_unstable(struct clocksource *cs) in clocksource_mark_unstable() argument
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/OK3568_Linux_fs/kernel/drivers/rkflash/
H A Dflash.c48 static void flash_read_id_raw(u8 cs, u8 *buf) in flash_read_id_raw() argument
52 nandc_flash_reset(cs); in flash_read_id_raw()
53 nandc_flash_cs(cs); in flash_read_id_raw()
54 nandc_writel(READ_ID_CMD, NANDC_CHIP_CMD(cs)); in flash_read_id_raw()
55 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); in flash_read_id_raw()
58 ptr[0] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
59 ptr[1] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
60 ptr[2] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
61 ptr[3] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
62 ptr[4] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
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/OK3568_Linux_fs/u-boot/drivers/rkflash/
H A Dflash.c47 static void flash_read_id_raw(u8 cs, u8 *buf) in flash_read_id_raw() argument
51 nandc_flash_reset(cs); in flash_read_id_raw()
52 nandc_flash_cs(cs); in flash_read_id_raw()
53 nandc_writel(READ_ID_CMD, NANDC_CHIP_CMD(cs)); in flash_read_id_raw()
54 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); in flash_read_id_raw()
57 ptr[0] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
58 ptr[1] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
59 ptr[2] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
60 ptr[3] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
61 ptr[4] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
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/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_write_leveling.c47 static int ddr3_write_leveling_single_cs(u32 cs, u32 freq, int ratio_2to1,
67 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
107 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw()
108 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_hw()
116 ddr3_read_pup_reg(PUP_WL_MODE, cs, in ddr3_write_leveling_hw()
122 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_hw()
123 dram_info->wl_val[cs][pup][D] = delay; in ddr3_write_leveling_hw()
124 dram_info->wl_val[cs][pup][S] = in ddr3_write_leveling_hw()
128 cs, pup); in ddr3_write_leveling_hw()
129 dram_info->wl_val[cs][pup][DQS] = in ddr3_write_leveling_hw()
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H A Dddr3_read_leveling.c45 static int ddr3_read_leveling_single_cs_rl_mode(u32 cs, u32 freq,
49 static int ddr3_read_leveling_single_cs_window_mode(u32 cs, u32 freq,
74 /* Enable CS in the automatic process */ in ddr3_read_leveling_hw()
92 u32 delay, phase, pup, cs; in ddr3_read_leveling_hw() local
98 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_read_leveling_hw()
99 if (dram_info->cs_ena & (1 << cs)) { in ddr3_read_leveling_hw()
107 ddr3_read_pup_reg(PUP_RL_MODE, cs, in ddr3_read_leveling_hw()
112 dram_info->rl_val[cs][pup][P] = phase; in ddr3_read_leveling_hw()
117 dram_info->rl_val[cs][pup][D] = delay; in ddr3_read_leveling_hw()
118 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
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/OK3568_Linux_fs/u-boot/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c79 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
80 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
81 .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
82 .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
83 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
84 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
85 .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
86 .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
87 .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
111 .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
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/OK3568_Linux_fs/external/xserver/composite/
H A Dcompinit.c58 CompScreenPtr cs = GetCompScreen(pScreen); in compCloseScreen() local
61 free(cs->alternateVisuals); in compCloseScreen()
63 pScreen->CloseScreen = cs->CloseScreen; in compCloseScreen()
64 pScreen->InstallColormap = cs->InstallColormap; in compCloseScreen()
65 pScreen->ChangeWindowAttributes = cs->ChangeWindowAttributes; in compCloseScreen()
66 pScreen->ReparentWindow = cs->ReparentWindow; in compCloseScreen()
67 pScreen->ConfigNotify = cs->ConfigNotify; in compCloseScreen()
68 pScreen->MoveWindow = cs->MoveWindow; in compCloseScreen()
69 pScreen->ResizeWindow = cs->ResizeWindow; in compCloseScreen()
70 pScreen->ChangeBorderWidth = cs->ChangeBorderWidth; in compCloseScreen()
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/OK3568_Linux_fs/kernel/drivers/scsi/
H A Dmyrs.c104 static void myrs_qcmd(struct myrs_hba *cs, struct myrs_cmdblk *cmd_blk) in myrs_qcmd() argument
106 void __iomem *base = cs->io_base; in myrs_qcmd()
108 union myrs_cmd_mbox *next_mbox = cs->next_cmd_mbox; in myrs_qcmd()
110 cs->write_cmd_mbox(next_mbox, mbox); in myrs_qcmd()
112 if (cs->prev_cmd_mbox1->words[0] == 0 || in myrs_qcmd()
113 cs->prev_cmd_mbox2->words[0] == 0) in myrs_qcmd()
114 cs->get_cmd_mbox(base); in myrs_qcmd()
116 cs->prev_cmd_mbox2 = cs->prev_cmd_mbox1; in myrs_qcmd()
117 cs->prev_cmd_mbox1 = next_mbox; in myrs_qcmd()
119 if (++next_mbox > cs->last_cmd_mbox) in myrs_qcmd()
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/OK3568_Linux_fs/kernel/drivers/misc/habanalabs/common/
H A Dcommand_submission.c49 /* EBUSY means the CS was never submitted and hence we don't have in hl_fence_release()
59 "CS 0x%llx type %d finished, sob_id: %d, sob_val: 0x%x\n", in hl_fence_release()
66 * A signal CS can get completion while the corresponding wait in hl_fence_release()
67 * for signal CS is on its way to the PQ. The wait for signal CS in hl_fence_release()
68 * will get stuck if the signal CS incremented the SOB to its in hl_fence_release()
72 * 1. The wait for signal CS must get a ref for the signal CS as in hl_fence_release()
76 * 2. Signal/Wait for signal CS will decrement the SOB refcnt in hl_fence_release()
78 * These two measures guarantee that the wait for signal CS will in hl_fence_release()
79 * reset the SOB upon completion rather than the signal CS and in hl_fence_release()
108 static void cs_get(struct hl_cs *cs) in cs_get() argument
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/OK3568_Linux_fs/kernel/drivers/memory/
H A Dstm32-fmc2-ebi.c170 const struct stm32_fmc2_prop *prop, int cs);
171 u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup);
174 int cs, u32 setup);
179 int cs) in stm32_fmc2_ebi_check_mux() argument
183 regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_mux()
193 int cs) in stm32_fmc2_ebi_check_waitcfg() argument
197 regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_waitcfg()
207 int cs) in stm32_fmc2_ebi_check_sync_trans() argument
211 regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_sync_trans()
221 int cs) in stm32_fmc2_ebi_check_async_trans() argument
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H A Domap-gpmc.c203 /* Structure to save gpmc cs context */
263 void gpmc_cs_write_reg(int cs, int idx, u32 val) in gpmc_cs_write_reg() argument
267 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; in gpmc_cs_write_reg()
271 static u32 gpmc_cs_read_reg(int cs, int idx) in gpmc_cs_read_reg() argument
275 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; in gpmc_cs_read_reg()
292 * @cs: Chip Select Region.
295 * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
298 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd) in gpmc_get_clk_period() argument
307 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); in gpmc_get_clk_period()
320 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs, in gpmc_ns_to_clk_ticks() argument
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/OK3568_Linux_fs/kernel/kernel/cgroup/
H A Dcpuset.c208 static inline struct cpuset *parent_cs(struct cpuset *cs) in parent_cs() argument
210 return css_cs(cs->css.parent); in parent_cs()
226 static inline bool is_cpuset_online(struct cpuset *cs) in is_cpuset_online() argument
228 return test_bit(CS_ONLINE, &cs->flags) && !css_is_dying(&cs->css); in is_cpuset_online()
231 static inline int is_cpu_exclusive(const struct cpuset *cs) in is_cpu_exclusive() argument
233 return test_bit(CS_CPU_EXCLUSIVE, &cs->flags); in is_cpu_exclusive()
236 static inline int is_mem_exclusive(const struct cpuset *cs) in is_mem_exclusive() argument
238 return test_bit(CS_MEM_EXCLUSIVE, &cs->flags); in is_mem_exclusive()
241 static inline int is_mem_hardwall(const struct cpuset *cs) in is_mem_hardwall() argument
243 return test_bit(CS_MEM_HARDWALL, &cs->flags); in is_mem_hardwall()
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/OK3568_Linux_fs/kernel/drivers/mfd/
H A Datmel-smc.c15 * atmel_smc_cs_conf_init - initialize a SMC CS conf
16 * @conf: the SMC CS conf to initialize
79 * atmel_smc_cs_conf_set_timing - set the SMC CS conf Txx parameter to a
81 * @conf: SMC CS conf descriptor
121 * atmel_smc_cs_conf_set_setup - set the SMC CS conf xx_SETUP parameter to a
123 * @conf: SMC CS conf descriptor
160 * atmel_smc_cs_conf_set_pulse - set the SMC CS conf xx_PULSE parameter to a
162 * @conf: SMC CS conf descriptor
199 * atmel_smc_cs_conf_set_cycle - set the SMC CS conf xx_CYCLE parameter to a
201 * @conf: SMC CS conf descriptor
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/OK3568_Linux_fs/kernel/sound/core/
H A Dpcm_iec958.c14 * @cs: channel status buffer, at least four bytes
17 * Create the consumer format channel status data in @cs of maximum size
29 int snd_pcm_create_iec958_consumer_default(u8 *cs, size_t len) in snd_pcm_create_iec958_consumer_default() argument
34 memset(cs, 0, len); in snd_pcm_create_iec958_consumer_default()
36 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE; in snd_pcm_create_iec958_consumer_default()
37 cs[1] = IEC958_AES1_CON_GENERAL; in snd_pcm_create_iec958_consumer_default()
38 cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC; in snd_pcm_create_iec958_consumer_default()
39 cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_NOTID; in snd_pcm_create_iec958_consumer_default()
42 cs[4] = IEC958_AES4_CON_WORDLEN_NOTID; in snd_pcm_create_iec958_consumer_default()
49 u8 *cs, size_t len) in fill_iec958_consumer() argument
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/OK3568_Linux_fs/kernel/fs/fuse/
H A Ddev.c668 static void fuse_copy_init(struct fuse_copy_state *cs, int write, in fuse_copy_init() argument
671 memset(cs, 0, sizeof(*cs)); in fuse_copy_init()
672 cs->write = write; in fuse_copy_init()
673 cs->iter = iter; in fuse_copy_init()
677 static void fuse_copy_finish(struct fuse_copy_state *cs) in fuse_copy_finish() argument
679 if (cs->currbuf) { in fuse_copy_finish()
680 struct pipe_buffer *buf = cs->currbuf; in fuse_copy_finish()
682 if (cs->write) in fuse_copy_finish()
683 buf->len = PAGE_SIZE - cs->len; in fuse_copy_finish()
684 cs->currbuf = NULL; in fuse_copy_finish()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/
H A Dti-aemif.txt34 - CS-specific partition/range. If continuous, must be
38 - control partition which is common for all CS
56 Child chip-select (cs) nodes contain the memory devices nodes connected to
60 Required child cs node properties:
73 - ti,cs-chipselect: number of chipselect. Indicates on the aemif driver
79 Optional child cs node properties:
81 - ti,cs-bus-width: width of the asynchronous device's data bus
84 - ti,cs-select-strobe-mode: enable/disable select strobe mode
89 - ti,cs-extended-wait-mode: enable/disable extended wait mode
95 - ti,cs-min-turnaround-ns: minimum turn around time, ns
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/OK3568_Linux_fs/u-boot/arch/arm/mach-omap2/omap3/
H A Dsdrc.c41 if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR) in is_mem_sdr()
69 u32 get_sdr_cs_size(u32 cs) in get_sdr_cs_size() argument
74 size = readl(&sdrc_base->cs[cs].mcfg) >> 8; in get_sdr_cs_size()
82 * - Get offset of cs from cs0 start
84 u32 get_sdr_cs_offset(u32 cs) in get_sdr_cs_offset() argument
88 if (!cs) in get_sdr_cs_offset()
99 * - Takes CS and associated timings and initalize SDRAM
100 * - Test CS to make sure it's OK for use
102 static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base, in write_sdrc_timings() argument
106 writel(timings->mcfg, &sdrc_base->cs[cs].mcfg); in write_sdrc_timings()
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/OK3568_Linux_fs/kernel/arch/m68k/include/asm/
H A Dm5307sim.h51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
59 #define MCFSIM_CSBAR (MCF_MBAR + 0x98) /* CS Base Address */
60 #define MCFSIM_CSBAMR (MCF_MBAR + 0x9c) /* CS Base Mask */
61 #define MCFSIM_CSMR2 (MCF_MBAR + 0x9e) /* CS 2 Mask reg */
62 #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
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/OK3568_Linux_fs/kernel/tools/perf/util/
H A Dcomm.c22 static struct comm_str *comm_str__get(struct comm_str *cs) in comm_str__get() argument
24 if (cs && refcount_inc_not_zero(&cs->refcnt)) in comm_str__get()
25 return cs; in comm_str__get()
30 static void comm_str__put(struct comm_str *cs) in comm_str__put() argument
32 if (cs && refcount_dec_and_test(&cs->refcnt)) { in comm_str__put()
34 rb_erase(&cs->rb_node, &comm_str_root); in comm_str__put()
36 zfree(&cs->str); in comm_str__put()
37 free(cs); in comm_str__put()
43 struct comm_str *cs; in comm_str__alloc() local
45 cs = zalloc(sizeof(*cs)); in comm_str__alloc()
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/OK3568_Linux_fs/kernel/arch/mips/bcm63xx/
H A Dcs.c24 static int is_valid_cs(unsigned int cs) in is_valid_cs() argument
26 if (cs > 6) in is_valid_cs()
35 int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size) in bcm63xx_set_cs_base() argument
40 if (!is_valid_cs(cs)) in bcm63xx_set_cs_base()
55 bcm_mpi_writel(val, MPI_CSBASE_REG(cs)); in bcm63xx_set_cs_base()
66 int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait, in bcm63xx_set_cs_timing() argument
72 if (!is_valid_cs(cs)) in bcm63xx_set_cs_timing()
76 val = bcm_mpi_readl(MPI_CSCTL_REG(cs)); in bcm63xx_set_cs_timing()
83 bcm_mpi_writel(val, MPI_CSCTL_REG(cs)); in bcm63xx_set_cs_timing()
94 int bcm63xx_set_cs_param(unsigned int cs, u32 params) in bcm63xx_set_cs_param() argument
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/OK3568_Linux_fs/kernel/include/linux/mfd/syscon/
H A Datmel-smc.h18 #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10)) argument
19 #define ATMEL_HSMC_SETUP(layout, cs) \ argument
20 ((layout)->timing_regs_offset + ((cs) * 0x14))
21 #define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4) argument
22 #define ATMEL_HSMC_PULSE(layout, cs) \ argument
23 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4)
24 #define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8) argument
25 #define ATMEL_HSMC_CYCLE(layout, cs) \ argument
26 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x8)
32 #define ATMEL_SMC_MODE(cs) (((cs) * 0x10) + 0xc) argument
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