1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public
3*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive
4*4882a593Smuzhiyun * for more details.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/errno.h>
11*4882a593Smuzhiyun #include <linux/export.h>
12*4882a593Smuzhiyun #include <linux/spinlock.h>
13*4882a593Smuzhiyun #include <linux/log2.h>
14*4882a593Smuzhiyun #include <bcm63xx_cpu.h>
15*4882a593Smuzhiyun #include <bcm63xx_io.h>
16*4882a593Smuzhiyun #include <bcm63xx_regs.h>
17*4882a593Smuzhiyun #include <bcm63xx_cs.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun static DEFINE_SPINLOCK(bcm63xx_cs_lock);
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /*
22*4882a593Smuzhiyun * check if given chip select exists
23*4882a593Smuzhiyun */
is_valid_cs(unsigned int cs)24*4882a593Smuzhiyun static int is_valid_cs(unsigned int cs)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun if (cs > 6)
27*4882a593Smuzhiyun return 0;
28*4882a593Smuzhiyun return 1;
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /*
32*4882a593Smuzhiyun * Configure chipselect base address and size (bytes).
33*4882a593Smuzhiyun * Size must be a power of two between 8k and 256M.
34*4882a593Smuzhiyun */
bcm63xx_set_cs_base(unsigned int cs,u32 base,unsigned int size)35*4882a593Smuzhiyun int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun unsigned long flags;
38*4882a593Smuzhiyun u32 val;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun if (!is_valid_cs(cs))
41*4882a593Smuzhiyun return -EINVAL;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /* sanity check on size */
44*4882a593Smuzhiyun if (size != roundup_pow_of_two(size))
45*4882a593Smuzhiyun return -EINVAL;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun if (size < 8 * 1024 || size > 256 * 1024 * 1024)
48*4882a593Smuzhiyun return -EINVAL;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun val = (base & MPI_CSBASE_BASE_MASK);
51*4882a593Smuzhiyun /* 8k => 0 - 256M => 15 */
52*4882a593Smuzhiyun val |= (ilog2(size) - ilog2(8 * 1024)) << MPI_CSBASE_SIZE_SHIFT;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun spin_lock_irqsave(&bcm63xx_cs_lock, flags);
55*4882a593Smuzhiyun bcm_mpi_writel(val, MPI_CSBASE_REG(cs));
56*4882a593Smuzhiyun spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun return 0;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun EXPORT_SYMBOL(bcm63xx_set_cs_base);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /*
64*4882a593Smuzhiyun * configure chipselect timing (ns)
65*4882a593Smuzhiyun */
bcm63xx_set_cs_timing(unsigned int cs,unsigned int wait,unsigned int setup,unsigned int hold)66*4882a593Smuzhiyun int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait,
67*4882a593Smuzhiyun unsigned int setup, unsigned int hold)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun unsigned long flags;
70*4882a593Smuzhiyun u32 val;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun if (!is_valid_cs(cs))
73*4882a593Smuzhiyun return -EINVAL;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun spin_lock_irqsave(&bcm63xx_cs_lock, flags);
76*4882a593Smuzhiyun val = bcm_mpi_readl(MPI_CSCTL_REG(cs));
77*4882a593Smuzhiyun val &= ~(MPI_CSCTL_WAIT_MASK);
78*4882a593Smuzhiyun val &= ~(MPI_CSCTL_SETUP_MASK);
79*4882a593Smuzhiyun val &= ~(MPI_CSCTL_HOLD_MASK);
80*4882a593Smuzhiyun val |= wait << MPI_CSCTL_WAIT_SHIFT;
81*4882a593Smuzhiyun val |= setup << MPI_CSCTL_SETUP_SHIFT;
82*4882a593Smuzhiyun val |= hold << MPI_CSCTL_HOLD_SHIFT;
83*4882a593Smuzhiyun bcm_mpi_writel(val, MPI_CSCTL_REG(cs));
84*4882a593Smuzhiyun spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun return 0;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun EXPORT_SYMBOL(bcm63xx_set_cs_timing);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun /*
92*4882a593Smuzhiyun * configure other chipselect parameter (data bus size, ...)
93*4882a593Smuzhiyun */
bcm63xx_set_cs_param(unsigned int cs,u32 params)94*4882a593Smuzhiyun int bcm63xx_set_cs_param(unsigned int cs, u32 params)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun unsigned long flags;
97*4882a593Smuzhiyun u32 val;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun if (!is_valid_cs(cs))
100*4882a593Smuzhiyun return -EINVAL;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /* none of this fields apply to pcmcia */
103*4882a593Smuzhiyun if (cs == MPI_CS_PCMCIA_COMMON ||
104*4882a593Smuzhiyun cs == MPI_CS_PCMCIA_ATTR ||
105*4882a593Smuzhiyun cs == MPI_CS_PCMCIA_IO)
106*4882a593Smuzhiyun return -EINVAL;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun spin_lock_irqsave(&bcm63xx_cs_lock, flags);
109*4882a593Smuzhiyun val = bcm_mpi_readl(MPI_CSCTL_REG(cs));
110*4882a593Smuzhiyun val &= ~(MPI_CSCTL_DATA16_MASK);
111*4882a593Smuzhiyun val &= ~(MPI_CSCTL_SYNCMODE_MASK);
112*4882a593Smuzhiyun val &= ~(MPI_CSCTL_TSIZE_MASK);
113*4882a593Smuzhiyun val &= ~(MPI_CSCTL_ENDIANSWAP_MASK);
114*4882a593Smuzhiyun val |= params;
115*4882a593Smuzhiyun bcm_mpi_writel(val, MPI_CSCTL_REG(cs));
116*4882a593Smuzhiyun spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun return 0;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun EXPORT_SYMBOL(bcm63xx_set_cs_param);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun /*
124*4882a593Smuzhiyun * set cs status (enable/disable)
125*4882a593Smuzhiyun */
bcm63xx_set_cs_status(unsigned int cs,int enable)126*4882a593Smuzhiyun int bcm63xx_set_cs_status(unsigned int cs, int enable)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun unsigned long flags;
129*4882a593Smuzhiyun u32 val;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun if (!is_valid_cs(cs))
132*4882a593Smuzhiyun return -EINVAL;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun spin_lock_irqsave(&bcm63xx_cs_lock, flags);
135*4882a593Smuzhiyun val = bcm_mpi_readl(MPI_CSCTL_REG(cs));
136*4882a593Smuzhiyun if (enable)
137*4882a593Smuzhiyun val |= MPI_CSCTL_ENABLE_MASK;
138*4882a593Smuzhiyun else
139*4882a593Smuzhiyun val &= ~MPI_CSCTL_ENABLE_MASK;
140*4882a593Smuzhiyun bcm_mpi_writel(val, MPI_CSCTL_REG(cs));
141*4882a593Smuzhiyun spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
142*4882a593Smuzhiyun return 0;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun EXPORT_SYMBOL(bcm63xx_set_cs_status);
146