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/OK3568_Linux_fs/u-boot/include/configs/
H A Devb_rk3568.h16 "stdin=serial,usbkbd\0" \
17 "stdout=serial,vidconsole\0" \
18 "stderr=serial,vidconsole\0"
20 #define CONFIG_SYS_MMC_ENV_DEV 0
30 "gpt raw 0x0 0x20000;" \
31 "loader raw 0x20000 0xE0000;"\
32 "uboot part 0 1;" \
33 "boot part 0 2;" \
34 "rootfs part 0 3;" \
35 "userdata part 0 4\0"
[all …]
H A Dok3568.h17 "stdin=serial,usbkbd\0" \
18 "stdout=serial,vidconsole\0" \
19 "stderr=serial,vidconsole\0"
21 #define CONFIG_SYS_MMC_ENV_DEV 0
31 "gpt raw 0x0 0x20000;" \
32 "loader raw 0x20000 0xE0000;"\
33 "uboot part 0 1;" \
34 "boot part 0 2;" \
35 "rootfs part 0 3;" \
36 "userdata part 0 4\0"
[all …]
H A Devb_rv1126.h12 #define CONFIG_SYS_MMC_ENV_DEV 0
15 "stdout=serial,vidconsole\0" \
16 "stderr=serial,vidconsole\0"
44 "gpt raw 0x0 0x20000;" \
45 "loader raw 0x20000 0xE0000;"\
46 "uboot part 0 1;" \
47 "boot part 0 2;" \
48 "rootfs partubi 0 3;" \
49 "userdata partubi 0 4\0"
53 "gpt raw 0x0 0x20000;" \
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dimx28-apf28.dts15 reg = <0x40000000 0x08000000>;
22 pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
25 partition@0 {
27 reg = <0x0 0x300000>;
32 reg = <0x300000 0x80000>;
37 reg = <0x380000 0x80000>;
42 reg = <0x400000 0x80000>;
47 reg = <0x480000 0x80000>;
52 reg = <0x500000 0x800000>;
57 reg = <0xd00000 0xf300000>;
[all …]
H A Darmada-xp-linksys-mamba.dts6 * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
34 memory@0 {
36 reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */
40 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
41 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
42 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
43 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
44 MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
64 pinctrl-0 = <&ge0_rgmii_pins>;
69 bm,pool-long = <0>;
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/imx/
H A Dclk-imx8qxp-lpcg.h11 #define LSIO_PWM_0_LPCG 0x00000
12 #define LSIO_PWM_1_LPCG 0x10000
13 #define LSIO_PWM_2_LPCG 0x20000
14 #define LSIO_PWM_3_LPCG 0x30000
15 #define LSIO_PWM_4_LPCG 0x40000
16 #define LSIO_PWM_5_LPCG 0x50000
17 #define LSIO_PWM_6_LPCG 0x60000
18 #define LSIO_PWM_7_LPCG 0x70000
19 #define LSIO_GPIO_0_LPCG 0x80000
20 #define LSIO_GPIO_1_LPCG 0x90000
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpu_sun9i.h13 #define REGS_AHB0_BASE 0x01C00000
14 #define REGS_AHB1_BASE 0x00800000
15 #define REGS_AHB2_BASE 0x03000000
16 #define REGS_APB0_BASE 0x06000000
17 #define REGS_APB1_BASE 0x07000000
18 #define REGS_RCPUS_BASE 0x08000000
20 #define SUNXI_SRAM_D_BASE 0x08100000
23 #define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
24 #define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
26 #define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/intel/iwlwifi/
H A Diwl-io.h76 iwl_trans_set_bits_mask(trans, reg, mask, 0); in iwl_clear_bit()
109 * UMAC periphery address space changed from 0xA00000 to 0xD00000 starting from
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/qcom/
H A Dipq8074.dtsi17 #clock-cells = <0>;
23 #clock-cells = <0>;
28 #address-cells = <0x1>;
29 #size-cells = <0x0>;
31 CPU0: cpu@0 {
34 reg = <0x0>;
43 reg = <0x1>;
51 reg = <0x2>;
59 reg = <0x3>;
65 cache-level = <0x2>;
[all …]
H A Dmsm8996.dtsi22 #clock-cells = <0>;
29 #clock-cells = <0>;
37 #size-cells = <0>;
39 CPU0: cpu@0 {
42 reg = <0x0 0x0>;
56 reg = <0x0 0x1>;
66 reg = <0x0 0x100>;
80 reg = <0x0 0x101>;
112 CPU_SLEEP_0: cpu-sleep-0 {
115 arm,psci-suspend-param = <0x00000004>;
[all …]
H A Dmsm8998.dtsi14 qcom,msm-id = <292 0x0>;
24 reg = <0 0 0 0>;
33 reg = <0x0 0x85800000 0x0 0x600000>;
38 reg = <0x0 0x85e00000 0x0 0x100000>;
43 reg = <0x0 0x86000000 0x0 0x200000>;
48 reg = <0x0 0x86200000 0x0 0x2d00000>;
54 reg = <0x0 0x88f00000 0x0 0x200000>;
62 reg = <0x0 0x8ab00000 0x0 0x700000>;
67 reg = <0x0 0x8b200000 0x0 0x1a00000>;
72 reg = <0x0 0x8cc00000 0x0 0x7000000>;
[all …]
H A Dsdm845.dtsi73 reg = <0 0x80000000 0 0>;
82 reg = <0 0x85700000 0 0x600000>;
87 reg = <0 0x85e00000 0 0x100000>;
92 reg = <0 0x85fc0000 0 0x20000>;
98 reg = <0x0 0x85fe0000 0 0x20000>;
103 reg = <0x0 0x86000000 0 0x200000>;
108 reg = <0 0x86200000 0 0x2d00000>;
114 reg = <0 0x88f00000 0 0x200000>;
122 reg = <0 0x8ab00000 0 0x1400000>;
127 reg = <0 0x8bf00000 0 0x500000>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/iommu/
H A Darm,smmu.yaml23 pattern: "^iommu@[0-9a-f]*"
80 minimum: 0
180 reg = <0xba5e0000 0x10000>;
182 interrupts = <0 32 4>,
183 <0 33 4>,
184 <0 34 4>, /* This is the first context interrupt */
185 <0 35 4>,
186 <0 36 4>,
187 <0 37 4>;
191 /* device with two stream IDs, 0 and 7 */
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/marvell/
H A Darmada-8040-db.dts20 memory@0 {
22 reg = <0x0 0x0 0x0 0x80000000>;
34 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
40 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
52 cp0_usb3_0_phy: cp0-usb3-0-phy {
57 cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
63 gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
66 cp1_usb3_0_phy: cp1-usb3-0-phy {
75 spi-flash@0 {
77 reg = <0>;
[all …]
/OK3568_Linux_fs/kernel/drivers/input/touchscreen/focaltech_touch_ft5436/
H A Dfocaltech_flash.h24 #define FTS_CMD_RESET 0x07
25 #define FTS_ROMBOOT_CMD_SET_PRAM_ADDR 0xAD
27 #define FTS_ROMBOOT_CMD_WRITE 0xAE
28 #define FTS_ROMBOOT_CMD_START_APP 0x08
30 #define FTS_ROMBOOT_CMD_ECC 0xCC
31 #define FTS_PRAM_SADDR 0x000000
32 #define FTS_DRAM_SADDR 0xD00000
34 #define FTS_CMD_READ 0x03
37 #define FTS_CMD_FLASH_TYPE 0x05
38 #define FTS_CMD_FLASH_MODE 0x09
[all …]
/OK3568_Linux_fs/kernel/arch/mips/include/asm/
H A Dcpu.h16 register 15, select 0) is defined in this (backwards compatible) way:
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
28 #define PRID_OPT_MASK 0xff000000
34 #define PRID_COMP_MASK 0xff0000
36 #define PRID_COMP_LEGACY 0x000000
37 #define PRID_COMP_MIPS 0x010000
38 #define PRID_COMP_BROADCOM 0x020000
39 #define PRID_COMP_ALCHEMY 0x030000
40 #define PRID_COMP_SIBYTE 0x040000
41 #define PRID_COMP_SANDCRAFT 0x050000
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/emulex/benet/
H A Dbe_cmds.h28 #define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
29 #define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
30 #define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
32 u32 embedded; /* dword 0 */
50 MCC_STATUS_SUCCESS = 0,
63 MCC_ADDL_STATUS_INSUFFICIENT_RESOURCES = 0x16,
64 MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH = 0x4d,
65 MCC_ADDL_STATUS_TOO_MANY_INTERFACES = 0x4a,
66 MCC_ADDL_STATUS_INSUFFICIENT_VLANS = 0xab,
67 MCC_ADDL_STATUS_INVALID_SIGNATURE = 0x56,
[all …]