1*4882a593Smuzhiyun /******************************************************************************
2*4882a593Smuzhiyun *
3*4882a593Smuzhiyun * This file is provided under a dual BSD/GPLv2 license. When using or
4*4882a593Smuzhiyun * redistributing this file, you may do so under either license.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * GPL LICENSE SUMMARY
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Copyright (C) 2018 - 2019 Intel Corporation
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it
11*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as
12*4882a593Smuzhiyun * published by the Free Software Foundation.
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT
15*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17*4882a593Smuzhiyun * more details.
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * The full GNU General Public License is included in this distribution in the
20*4882a593Smuzhiyun * file called COPYING.
21*4882a593Smuzhiyun *
22*4882a593Smuzhiyun * Contact Information:
23*4882a593Smuzhiyun * Intel Linux Wireless <linuxwifi@intel.com>
24*4882a593Smuzhiyun * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25*4882a593Smuzhiyun *
26*4882a593Smuzhiyun * BSD LICENSE
27*4882a593Smuzhiyun *
28*4882a593Smuzhiyun * Copyright (C) 2018 - 2019 Intel Corporation
29*4882a593Smuzhiyun * All rights reserved.
30*4882a593Smuzhiyun *
31*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or without
32*4882a593Smuzhiyun * modification, are permitted provided that the following conditions
33*4882a593Smuzhiyun * are met:
34*4882a593Smuzhiyun *
35*4882a593Smuzhiyun * * Redistributions of source code must retain the above copyright
36*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer.
37*4882a593Smuzhiyun * * Redistributions in binary form must reproduce the above copyright
38*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer in
39*4882a593Smuzhiyun * the documentation and/or other materials provided with the
40*4882a593Smuzhiyun * distribution.
41*4882a593Smuzhiyun * * Neither the name Intel Corporation nor the names of its
42*4882a593Smuzhiyun * contributors may be used to endorse or promote products derived
43*4882a593Smuzhiyun * from this software without specific prior written permission.
44*4882a593Smuzhiyun *
45*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
46*4882a593Smuzhiyun * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
47*4882a593Smuzhiyun * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
48*4882a593Smuzhiyun * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
49*4882a593Smuzhiyun * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
50*4882a593Smuzhiyun * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
51*4882a593Smuzhiyun * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
52*4882a593Smuzhiyun * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
53*4882a593Smuzhiyun * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
54*4882a593Smuzhiyun * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
55*4882a593Smuzhiyun * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
56*4882a593Smuzhiyun *
57*4882a593Smuzhiyun *****************************************************************************/
58*4882a593Smuzhiyun #ifndef __iwl_io_h__
59*4882a593Smuzhiyun #define __iwl_io_h__
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun #include "iwl-devtrace.h"
62*4882a593Smuzhiyun #include "iwl-trans.h"
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun void iwl_write8(struct iwl_trans *trans, u32 ofs, u8 val);
65*4882a593Smuzhiyun void iwl_write32(struct iwl_trans *trans, u32 ofs, u32 val);
66*4882a593Smuzhiyun void iwl_write64(struct iwl_trans *trans, u64 ofs, u64 val);
67*4882a593Smuzhiyun u32 iwl_read32(struct iwl_trans *trans, u32 ofs);
68*4882a593Smuzhiyun
iwl_set_bit(struct iwl_trans * trans,u32 reg,u32 mask)69*4882a593Smuzhiyun static inline void iwl_set_bit(struct iwl_trans *trans, u32 reg, u32 mask)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun iwl_trans_set_bits_mask(trans, reg, mask, mask);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
iwl_clear_bit(struct iwl_trans * trans,u32 reg,u32 mask)74*4882a593Smuzhiyun static inline void iwl_clear_bit(struct iwl_trans *trans, u32 reg, u32 mask)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun iwl_trans_set_bits_mask(trans, reg, mask, 0);
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun int iwl_poll_bit(struct iwl_trans *trans, u32 addr,
80*4882a593Smuzhiyun u32 bits, u32 mask, int timeout);
81*4882a593Smuzhiyun int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask,
82*4882a593Smuzhiyun int timeout);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg);
85*4882a593Smuzhiyun void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value);
86*4882a593Smuzhiyun void iwl_write_direct64(struct iwl_trans *trans, u64 reg, u64 value);
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun u32 iwl_read_prph_no_grab(struct iwl_trans *trans, u32 ofs);
90*4882a593Smuzhiyun u32 iwl_read_prph(struct iwl_trans *trans, u32 ofs);
91*4882a593Smuzhiyun void iwl_write_prph_no_grab(struct iwl_trans *trans, u32 ofs, u32 val);
92*4882a593Smuzhiyun void iwl_write_prph64_no_grab(struct iwl_trans *trans, u64 ofs, u64 val);
93*4882a593Smuzhiyun void iwl_write_prph(struct iwl_trans *trans, u32 ofs, u32 val);
94*4882a593Smuzhiyun int iwl_poll_prph_bit(struct iwl_trans *trans, u32 addr,
95*4882a593Smuzhiyun u32 bits, u32 mask, int timeout);
96*4882a593Smuzhiyun void iwl_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask);
97*4882a593Smuzhiyun void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 ofs,
98*4882a593Smuzhiyun u32 bits, u32 mask);
99*4882a593Smuzhiyun void iwl_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask);
100*4882a593Smuzhiyun void iwl_force_nmi(struct iwl_trans *trans);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun int iwl_finish_nic_init(struct iwl_trans *trans,
103*4882a593Smuzhiyun const struct iwl_cfg_trans_params *cfg_trans);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /* Error handling */
106*4882a593Smuzhiyun int iwl_dump_fh(struct iwl_trans *trans, char **buf);
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /*
109*4882a593Smuzhiyun * UMAC periphery address space changed from 0xA00000 to 0xD00000 starting from
110*4882a593Smuzhiyun * device family AX200. So peripheries used in families above and below AX200
111*4882a593Smuzhiyun * should go through iwl_..._umac_..._prph.
112*4882a593Smuzhiyun */
iwl_umac_prph(struct iwl_trans * trans,u32 ofs)113*4882a593Smuzhiyun static inline u32 iwl_umac_prph(struct iwl_trans *trans, u32 ofs)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun return ofs + trans->trans_cfg->umac_prph_offset;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
iwl_read_umac_prph_no_grab(struct iwl_trans * trans,u32 ofs)118*4882a593Smuzhiyun static inline u32 iwl_read_umac_prph_no_grab(struct iwl_trans *trans, u32 ofs)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun return iwl_read_prph_no_grab(trans, ofs +
121*4882a593Smuzhiyun trans->trans_cfg->umac_prph_offset);
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
iwl_read_umac_prph(struct iwl_trans * trans,u32 ofs)124*4882a593Smuzhiyun static inline u32 iwl_read_umac_prph(struct iwl_trans *trans, u32 ofs)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun return iwl_read_prph(trans, ofs + trans->trans_cfg->umac_prph_offset);
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
iwl_write_umac_prph_no_grab(struct iwl_trans * trans,u32 ofs,u32 val)129*4882a593Smuzhiyun static inline void iwl_write_umac_prph_no_grab(struct iwl_trans *trans, u32 ofs,
130*4882a593Smuzhiyun u32 val)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun iwl_write_prph_no_grab(trans, ofs + trans->trans_cfg->umac_prph_offset,
133*4882a593Smuzhiyun val);
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun
iwl_write_umac_prph(struct iwl_trans * trans,u32 ofs,u32 val)136*4882a593Smuzhiyun static inline void iwl_write_umac_prph(struct iwl_trans *trans, u32 ofs,
137*4882a593Smuzhiyun u32 val)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun iwl_write_prph(trans, ofs + trans->trans_cfg->umac_prph_offset, val);
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
iwl_poll_umac_prph_bit(struct iwl_trans * trans,u32 addr,u32 bits,u32 mask,int timeout)142*4882a593Smuzhiyun static inline int iwl_poll_umac_prph_bit(struct iwl_trans *trans, u32 addr,
143*4882a593Smuzhiyun u32 bits, u32 mask, int timeout)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun return iwl_poll_prph_bit(trans, addr +
146*4882a593Smuzhiyun trans->trans_cfg->umac_prph_offset,
147*4882a593Smuzhiyun bits, mask, timeout);
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun #endif
151