1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2016 Marvell Technology Group Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Device Tree file for Marvell Armada 8040 Development board platform 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 9*4882a593Smuzhiyun#include "armada-8040.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "Marvell Armada 8040 DB board"; 13*4882a593Smuzhiyun compatible = "marvell,armada8040-db", "marvell,armada8040", 14*4882a593Smuzhiyun "marvell,armada-ap806-quad", "marvell,armada-ap806"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun chosen { 17*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun memory@0 { 21*4882a593Smuzhiyun device_type = "memory"; 22*4882a593Smuzhiyun reg = <0x0 0x0 0x0 0x80000000>; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun aliases { 26*4882a593Smuzhiyun ethernet0 = &cp0_eth0; 27*4882a593Smuzhiyun ethernet1 = &cp0_eth2; 28*4882a593Smuzhiyun ethernet2 = &cp1_eth0; 29*4882a593Smuzhiyun ethernet3 = &cp1_eth1; 30*4882a593Smuzhiyun i2c1 = &cp0_i2c0; 31*4882a593Smuzhiyun i2c2 = &cp1_i2c0; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { 35*4882a593Smuzhiyun compatible = "regulator-fixed"; 36*4882a593Smuzhiyun regulator-name = "cp0-usb3h0-vbus"; 37*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 38*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 39*4882a593Smuzhiyun enable-active-high; 40*4882a593Smuzhiyun gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus { 44*4882a593Smuzhiyun compatible = "regulator-fixed"; 45*4882a593Smuzhiyun regulator-name = "cp0-usb3h1-vbus"; 46*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 47*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 48*4882a593Smuzhiyun enable-active-high; 49*4882a593Smuzhiyun gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun cp0_usb3_0_phy: cp0-usb3-0-phy { 53*4882a593Smuzhiyun compatible = "usb-nop-xceiv"; 54*4882a593Smuzhiyun vcc-supply = <&cp0_reg_usb3_0_vbus>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus { 58*4882a593Smuzhiyun compatible = "regulator-fixed"; 59*4882a593Smuzhiyun regulator-name = "cp1-usb3h0-vbus"; 60*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 61*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 62*4882a593Smuzhiyun enable-active-high; 63*4882a593Smuzhiyun gpio = <&expander1 0 GPIO_ACTIVE_HIGH>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun cp1_usb3_0_phy: cp1-usb3-0-phy { 67*4882a593Smuzhiyun compatible = "usb-nop-xceiv"; 68*4882a593Smuzhiyun vcc-supply = <&cp1_reg_usb3_0_vbus>; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun}; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun&spi0 { 73*4882a593Smuzhiyun status = "okay"; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun spi-flash@0 { 76*4882a593Smuzhiyun compatible = "jedec,spi-nor"; 77*4882a593Smuzhiyun reg = <0>; 78*4882a593Smuzhiyun spi-max-frequency = <10000000>; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun partitions { 81*4882a593Smuzhiyun compatible = "fixed-partitions"; 82*4882a593Smuzhiyun #address-cells = <1>; 83*4882a593Smuzhiyun #size-cells = <1>; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun partition@0 { 86*4882a593Smuzhiyun label = "U-Boot"; 87*4882a593Smuzhiyun reg = <0 0x200000>; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun partition@400000 { 90*4882a593Smuzhiyun label = "Filesystem"; 91*4882a593Smuzhiyun reg = <0x200000 0xce0000>; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun}; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun/* Accessible over the mini-USB CON9 connector on the main board */ 98*4882a593Smuzhiyun&uart0 { 99*4882a593Smuzhiyun status = "okay"; 100*4882a593Smuzhiyun pinctrl-0 = <&uart0_pins>; 101*4882a593Smuzhiyun pinctrl-names = "default"; 102*4882a593Smuzhiyun}; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun/* CON6 on CP0 expansion */ 105*4882a593Smuzhiyun&cp0_pcie0 { 106*4882a593Smuzhiyun phys = <&cp0_comphy0 0>; 107*4882a593Smuzhiyun phy-names = "cp0-pcie0-x1-phy"; 108*4882a593Smuzhiyun status = "okay"; 109*4882a593Smuzhiyun}; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun/* CON5 on CP0 expansion */ 112*4882a593Smuzhiyun&cp0_pcie2 { 113*4882a593Smuzhiyun phys = <&cp0_comphy5 2>; 114*4882a593Smuzhiyun phy-names = "cp0-pcie2-x1-phy"; 115*4882a593Smuzhiyun status = "okay"; 116*4882a593Smuzhiyun}; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun&cp0_i2c0 { 119*4882a593Smuzhiyun status = "okay"; 120*4882a593Smuzhiyun clock-frequency = <100000>; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun /* U31 */ 123*4882a593Smuzhiyun expander0: pca9555@21 { 124*4882a593Smuzhiyun compatible = "nxp,pca9555"; 125*4882a593Smuzhiyun pinctrl-names = "default"; 126*4882a593Smuzhiyun gpio-controller; 127*4882a593Smuzhiyun #gpio-cells = <2>; 128*4882a593Smuzhiyun reg = <0x21>; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* U25 */ 132*4882a593Smuzhiyun expander1: pca9555@25 { 133*4882a593Smuzhiyun compatible = "nxp,pca9555"; 134*4882a593Smuzhiyun pinctrl-names = "default"; 135*4882a593Smuzhiyun gpio-controller; 136*4882a593Smuzhiyun #gpio-cells = <2>; 137*4882a593Smuzhiyun reg = <0x25>; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun}; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun/* CON4 on CP0 expansion */ 143*4882a593Smuzhiyun&cp0_sata0 { 144*4882a593Smuzhiyun status = "okay"; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun sata-port@0 { 147*4882a593Smuzhiyun phys = <&cp0_comphy1 0>; 148*4882a593Smuzhiyun phy-names = "cp0-sata0-0-phy"; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun sata-port@1 { 151*4882a593Smuzhiyun phys = <&cp0_comphy3 1>; 152*4882a593Smuzhiyun phy-names = "cp0-sata0-1-phy"; 153*4882a593Smuzhiyun }; 154*4882a593Smuzhiyun}; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun/* CON9 on CP0 expansion */ 157*4882a593Smuzhiyun&cp0_usb3_0 { 158*4882a593Smuzhiyun usb-phy = <&cp0_usb3_0_phy>; 159*4882a593Smuzhiyun status = "okay"; 160*4882a593Smuzhiyun}; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun&cp0_comphy4 { 163*4882a593Smuzhiyun cp0_usbh1_con: connector { 164*4882a593Smuzhiyun compatible = "usb-a-connector"; 165*4882a593Smuzhiyun phy-supply = <&cp0_reg_usb3_1_vbus>; 166*4882a593Smuzhiyun }; 167*4882a593Smuzhiyun}; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun/* CON10 on CP0 expansion */ 170*4882a593Smuzhiyun&cp0_usb3_1 { 171*4882a593Smuzhiyun phys = <&cp0_comphy4 1>; 172*4882a593Smuzhiyun phy-names = "cp0-usb3h1-comphy"; 173*4882a593Smuzhiyun status = "okay"; 174*4882a593Smuzhiyun}; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun&cp0_mdio { 177*4882a593Smuzhiyun status = "okay"; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun phy1: ethernet-phy@1 { 180*4882a593Smuzhiyun reg = <1>; 181*4882a593Smuzhiyun }; 182*4882a593Smuzhiyun}; 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun&cp0_ethernet { 185*4882a593Smuzhiyun status = "okay"; 186*4882a593Smuzhiyun}; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun&cp0_eth0 { 189*4882a593Smuzhiyun status = "okay"; 190*4882a593Smuzhiyun phy-mode = "10gbase-kr"; 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun fixed-link { 193*4882a593Smuzhiyun speed = <10000>; 194*4882a593Smuzhiyun full-duplex; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun}; 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun&cp0_eth2 { 199*4882a593Smuzhiyun status = "okay"; 200*4882a593Smuzhiyun phy = <&phy1>; 201*4882a593Smuzhiyun phy-mode = "rgmii-id"; 202*4882a593Smuzhiyun}; 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun/* CON6 on CP1 expansion */ 205*4882a593Smuzhiyun&cp1_pcie0 { 206*4882a593Smuzhiyun phys = <&cp1_comphy0 0>; 207*4882a593Smuzhiyun phy-names = "cp1-pcie0-x1-phy"; 208*4882a593Smuzhiyun status = "okay"; 209*4882a593Smuzhiyun}; 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun/* CON7 on CP1 expansion */ 212*4882a593Smuzhiyun&cp1_pcie1 { 213*4882a593Smuzhiyun phys = <&cp1_comphy4 1>; 214*4882a593Smuzhiyun phy-names = "cp1-pcie1-x1-phy"; 215*4882a593Smuzhiyun status = "okay"; 216*4882a593Smuzhiyun}; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun/* CON5 on CP1 expansion */ 219*4882a593Smuzhiyun&cp1_pcie2 { 220*4882a593Smuzhiyun phys = <&cp1_comphy5 2>; 221*4882a593Smuzhiyun phy-names = "cp1-pcie2-x1-phy"; 222*4882a593Smuzhiyun status = "okay"; 223*4882a593Smuzhiyun}; 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun&cp1_i2c0 { 226*4882a593Smuzhiyun status = "okay"; 227*4882a593Smuzhiyun clock-frequency = <100000>; 228*4882a593Smuzhiyun}; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun&cp1_spi1 { 231*4882a593Smuzhiyun status = "okay"; 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun spi-flash@0 { 234*4882a593Smuzhiyun compatible = "jedec,spi-nor"; 235*4882a593Smuzhiyun reg = <0x0>; 236*4882a593Smuzhiyun spi-max-frequency = <20000000>; 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun partitions { 239*4882a593Smuzhiyun compatible = "fixed-partitions"; 240*4882a593Smuzhiyun #address-cells = <1>; 241*4882a593Smuzhiyun #size-cells = <1>; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun partition@0 { 244*4882a593Smuzhiyun label = "Boot"; 245*4882a593Smuzhiyun reg = <0x0 0x200000>; 246*4882a593Smuzhiyun }; 247*4882a593Smuzhiyun partition@200000 { 248*4882a593Smuzhiyun label = "Filesystem"; 249*4882a593Smuzhiyun reg = <0x200000 0xd00000>; 250*4882a593Smuzhiyun }; 251*4882a593Smuzhiyun partition@f00000 { 252*4882a593Smuzhiyun label = "Boot_2nd"; 253*4882a593Smuzhiyun reg = <0xf00000 0x100000>; 254*4882a593Smuzhiyun }; 255*4882a593Smuzhiyun }; 256*4882a593Smuzhiyun }; 257*4882a593Smuzhiyun}; 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun/* 260*4882a593Smuzhiyun * Proper NAND usage will require DPR-76 to be in position 1-2, which disables 261*4882a593Smuzhiyun * MDIO signal of CP1. 262*4882a593Smuzhiyun */ 263*4882a593Smuzhiyun&cp1_nand_controller { 264*4882a593Smuzhiyun pinctrl-0 = <&nand_pins>, <&nand_rb>; 265*4882a593Smuzhiyun pinctrl-names = "default"; 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun nand@0 { 268*4882a593Smuzhiyun reg = <0>; 269*4882a593Smuzhiyun nand-rb = <0>; 270*4882a593Smuzhiyun nand-on-flash-bbt; 271*4882a593Smuzhiyun nand-ecc-strength = <4>; 272*4882a593Smuzhiyun nand-ecc-step-size = <512>; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun partitions { 275*4882a593Smuzhiyun compatible = "fixed-partitions"; 276*4882a593Smuzhiyun #address-cells = <1>; 277*4882a593Smuzhiyun #size-cells = <1>; 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun partition@0 { 280*4882a593Smuzhiyun label = "U-Boot"; 281*4882a593Smuzhiyun reg = <0 0x200000>; 282*4882a593Smuzhiyun }; 283*4882a593Smuzhiyun partition@200000 { 284*4882a593Smuzhiyun label = "Linux"; 285*4882a593Smuzhiyun reg = <0x200000 0xe00000>; 286*4882a593Smuzhiyun }; 287*4882a593Smuzhiyun partition@1000000 { 288*4882a593Smuzhiyun label = "Filesystem"; 289*4882a593Smuzhiyun reg = <0x1000000 0x3f000000>; 290*4882a593Smuzhiyun }; 291*4882a593Smuzhiyun }; 292*4882a593Smuzhiyun }; 293*4882a593Smuzhiyun}; 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun/* CON4 on CP1 expansion */ 296*4882a593Smuzhiyun&cp1_sata0 { 297*4882a593Smuzhiyun status = "okay"; 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun sata-port@0 { 300*4882a593Smuzhiyun phys = <&cp1_comphy1 0>; 301*4882a593Smuzhiyun phy-names = "cp1-sata0-0-phy"; 302*4882a593Smuzhiyun }; 303*4882a593Smuzhiyun sata-port@1 { 304*4882a593Smuzhiyun phys = <&cp1_comphy3 1>; 305*4882a593Smuzhiyun phy-names = "cp1-sata0-1-phy"; 306*4882a593Smuzhiyun }; 307*4882a593Smuzhiyun}; 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun/* CON9 on CP1 expansion */ 310*4882a593Smuzhiyun&cp1_usb3_0 { 311*4882a593Smuzhiyun usb-phy = <&cp1_usb3_0_phy>; 312*4882a593Smuzhiyun status = "okay"; 313*4882a593Smuzhiyun}; 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun/* CON10 on CP1 expansion */ 316*4882a593Smuzhiyun&cp1_usb3_1 { 317*4882a593Smuzhiyun status = "okay"; 318*4882a593Smuzhiyun}; 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun&cp1_mdio { 321*4882a593Smuzhiyun status = "okay"; 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun phy0: ethernet-phy@0 { 324*4882a593Smuzhiyun reg = <0>; 325*4882a593Smuzhiyun }; 326*4882a593Smuzhiyun}; 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun&cp1_ethernet { 329*4882a593Smuzhiyun status = "okay"; 330*4882a593Smuzhiyun}; 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun&cp1_eth0 { 333*4882a593Smuzhiyun status = "okay"; 334*4882a593Smuzhiyun phy-mode = "10gbase-kr"; 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun fixed-link { 337*4882a593Smuzhiyun speed = <10000>; 338*4882a593Smuzhiyun full-duplex; 339*4882a593Smuzhiyun }; 340*4882a593Smuzhiyun}; 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun&cp1_eth1 { 343*4882a593Smuzhiyun status = "okay"; 344*4882a593Smuzhiyun phy = <&phy0>; 345*4882a593Smuzhiyun phy-mode = "rgmii-id"; 346*4882a593Smuzhiyun}; 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun&ap_sdhci0 { 349*4882a593Smuzhiyun status = "okay"; 350*4882a593Smuzhiyun bus-width = <4>; 351*4882a593Smuzhiyun non-removable; 352*4882a593Smuzhiyun}; 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun&cp0_sdhci0 { 355*4882a593Smuzhiyun status = "okay"; 356*4882a593Smuzhiyun bus-width = <8>; 357*4882a593Smuzhiyun non-removable; 358*4882a593Smuzhiyun}; 359