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Searched refs:u8Clk (Results 1 – 14 of 14) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_dip.c1017 MS_U16 u8Clk = 0; in HAL_XC_DIP_MuxDispatch() local
1022 u8Clk = MDrv_Read2Byte(REG_CKG_IDCLK2); in HAL_XC_DIP_MuxDispatch()
1023 u8Clk = (u8Clk & CKG_IDCLK2_MASK ) >>CKG_IDCLK2_SHIFT; in HAL_XC_DIP_MuxDispatch()
1024 HAL_XC_DIP_SetMux(pInstance, SC_DWIN_IPMUX_SC_VOP, u8Clk<<CKG_IDCLK3_SHIFT ,eWindow); in HAL_XC_DIP_MuxDispatch()
1033 u8Clk = MDrv_ReadByte(REG_CKG_IDCLK1); in HAL_XC_DIP_MuxDispatch()
1034 u8Clk = (u8Clk & CKG_IDCLK1_MASK ); in HAL_XC_DIP_MuxDispatch()
1035 HAL_XC_DIP_SetMux(pInstance, SC_DWIN_IPMUX_IP_SUB,u8Clk,eWindow); in HAL_XC_DIP_MuxDispatch()
1068 u8Clk = MDrv_Read2Byte(REG_CKG_IDCLK2); in HAL_XC_DIP_MuxDispatch()
1069 u8Clk = (u8Clk & CKG_IDCLK2_MASK ) >>CKG_IDCLK2_SHIFT; in HAL_XC_DIP_MuxDispatch()
1070 HAL_XC_DIP_SetMux(pInstance, SC_DWIN_IPMUX_MVOP, u8Clk<<CKG_IDCLK3_SHIFT ,eWindow); in HAL_XC_DIP_MuxDispatch()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_dip.c1036 MS_U16 u8Clk = 0; in HAL_XC_DIP_MuxDispatch() local
1050 u8Clk = MDrv_ReadByte(REG_CKG_IDCLK1); in HAL_XC_DIP_MuxDispatch()
1051 u8Clk = (u8Clk & CKG_IDCLK1_MASK ); in HAL_XC_DIP_MuxDispatch()
1052 HAL_XC_DIP_SetMux(pInstance, SC_DWIN_IPMUX_IP_SUB,u8Clk,eWindow); in HAL_XC_DIP_MuxDispatch()
1108 u8Clk = MDrv_ReadByte(REG_CKG_IDCLK1); in HAL_XC_DIP_MuxDispatch()
1109 u8Clk = (u8Clk & CKG_IDCLK1_MASK ); in HAL_XC_DIP_MuxDispatch()
1110 HAL_XC_DIP_SetMux(pInstance, SC_DWIN_IPMUX_IP_SUB,u8Clk,eWindow); in HAL_XC_DIP_MuxDispatch()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A DhalPNL.c323 MS_U8 u8Clk = 0; in _MHal_PNL_Set_Clk() local
345 u8Clk = 0; in _MHal_PNL_Set_Clk()
356 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2]; in _MHal_PNL_Set_Clk()
357 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable in _MHal_PNL_Set_Clk()
377 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2]; in _MHal_PNL_Set_Clk()
378 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable in _MHal_PNL_Set_Clk()
398 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2]; in _MHal_PNL_Set_Clk()
399 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable in _MHal_PNL_Set_Clk()
420 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2]; in _MHal_PNL_Set_Clk()
421 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable in _MHal_PNL_Set_Clk()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A DhalPNL.c323 MS_U8 u8Clk = 0; in _MHal_PNL_Set_Clk() local
345 u8Clk = 0; in _MHal_PNL_Set_Clk()
356 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2]; in _MHal_PNL_Set_Clk()
357 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable in _MHal_PNL_Set_Clk()
377 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2]; in _MHal_PNL_Set_Clk()
378 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable in _MHal_PNL_Set_Clk()
398 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2]; in _MHal_PNL_Set_Clk()
399 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable in _MHal_PNL_Set_Clk()
420 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2]; in _MHal_PNL_Set_Clk()
421 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable in _MHal_PNL_Set_Clk()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A DhalPNL.c4036 MS_U8 u8Clk = 0; in _MHal_PNL_Set_Clk() local
4058 u8Clk = 0; in _MHal_PNL_Set_Clk()
4069 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2]; in _MHal_PNL_Set_Clk()
4070 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable in _MHal_PNL_Set_Clk()
4090 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2]; in _MHal_PNL_Set_Clk()
4091 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable in _MHal_PNL_Set_Clk()
4111 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2]; in _MHal_PNL_Set_Clk()
4112 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable in _MHal_PNL_Set_Clk()
4133 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2]; in _MHal_PNL_Set_Clk()
4134 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable in _MHal_PNL_Set_Clk()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A DhalPNL.c489 MS_U8 u8Clk = 0;
511 u8Clk = 0;
522 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2];
523 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable
543 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2];
544 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable
564 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2];
565 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable
586 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2];
587 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A DhalPNL.c490 MS_U8 u8Clk = 0;
512 u8Clk = 0;
523 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2];
524 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable
544 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2];
545 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable
565 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2];
566 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable
587 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2];
588 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A DhalPNL.c490 MS_U8 u8Clk = 0;
512 u8Clk = 0;
523 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2];
524 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable
544 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2];
545 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable
565 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2];
566 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable
587 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2];
588 u8Clk |= 0x01;//mod_a_reg38 [1]:clk enable
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_dip.c1201 MS_U8 u8Clk = 0; in HAL_XC_DIP_MuxDispatch() local
1206 u8Clk = MDrv_ReadByte(REG_CKG_IDCLK2); in HAL_XC_DIP_MuxDispatch()
1207 u8Clk = (u8Clk & CKG_IDCLK2_MASK ); in HAL_XC_DIP_MuxDispatch()
1212 u8Clk = MDrv_ReadByte(REG_CKG_IDCLK1); in HAL_XC_DIP_MuxDispatch()
1213 u8Clk = (u8Clk & CKG_IDCLK1_MASK ); in HAL_XC_DIP_MuxDispatch()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_dip.c1199 MS_U8 u8Clk = 0; in HAL_XC_DIP_MuxDispatch() local
1204 u8Clk = MDrv_ReadByte(REG_CKG_IDCLK2); in HAL_XC_DIP_MuxDispatch()
1205 u8Clk = (u8Clk & CKG_IDCLK2_MASK ); in HAL_XC_DIP_MuxDispatch()
1210 u8Clk = MDrv_ReadByte(REG_CKG_IDCLK1); in HAL_XC_DIP_MuxDispatch()
1211 u8Clk = (u8Clk & CKG_IDCLK1_MASK ); in HAL_XC_DIP_MuxDispatch()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_dip.c1294 MS_U8 u8Clk = 0; in HAL_XC_DIP_MuxDispatch() local
1299 u8Clk = MDrv_ReadByte(REG_CKG_IDCLK2); in HAL_XC_DIP_MuxDispatch()
1300 u8Clk = (u8Clk & CKG_IDCLK2_MASK ); in HAL_XC_DIP_MuxDispatch()
1305 u8Clk = MDrv_ReadByte(REG_CKG_IDCLK1); in HAL_XC_DIP_MuxDispatch()
1306 u8Clk = (u8Clk & CKG_IDCLK1_MASK ); in HAL_XC_DIP_MuxDispatch()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_dip.c1440 MS_U8 u8Clk = 0; in HAL_XC_DIP_MuxDispatch() local
1445 u8Clk = MDrv_ReadByte(REG_CKG_IDCLK2); in HAL_XC_DIP_MuxDispatch()
1446 u8Clk = (u8Clk & CKG_IDCLK2_MASK ); in HAL_XC_DIP_MuxDispatch()
1451 u8Clk = MDrv_ReadByte(REG_CKG_IDCLK1); in HAL_XC_DIP_MuxDispatch()
1452 u8Clk = (u8Clk & CKG_IDCLK1_MASK ); in HAL_XC_DIP_MuxDispatch()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A DhalPNL.c5729 MS_U8 u8Clk = 0; in _MHal_PNL_Set_Clk() local
5765 u8Clk = 0; in _MHal_PNL_Set_Clk()
5776 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2]; in _MHal_PNL_Set_Clk()
5796 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2]; in _MHal_PNL_Set_Clk()
5816 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2]; in _MHal_PNL_Set_Clk()
5837 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2]; in _MHal_PNL_Set_Clk()
5847 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, u8Clk, 0x1F); in _MHal_PNL_Set_Clk()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A DhalPNL.c5779 MS_U8 u8Clk = 0; in _MHal_PNL_Set_Clk() local
5815 u8Clk = 0; in _MHal_PNL_Set_Clk()
5826 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2]; in _MHal_PNL_Set_Clk()
5846 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2]; in _MHal_PNL_Set_Clk()
5866 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2]; in _MHal_PNL_Set_Clk()
5887 u8Clk |= LANE_AND_CLK_TBL[u8Count1][2]; in _MHal_PNL_Set_Clk()
5897 MOD_A_W2BYTEMSK(REG_MOD_A_BK00_00_L, u8Clk, 0x1F); in _MHal_PNL_Set_Clk()