| /utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/mhl/internal/ |
| H A D | halMHL.c | 410 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
411 … W2BYTEMSK(REG_COMBO_PHY0_P0_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_HdmiBypassModeSetting()
412 W2BYTEMSK(REG_COMBO_PHY0_P0_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
413 W2BYTEMSK(REG_HDCP_DUAL_P0_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
414 W2BYTEMSK(REG_COMBO_PHY0_P0_6F_L, 0, BIT(10)); // I-control PD overwrite write in _mhal_mhl_HdmiBypassModeSetting()
415 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
416 W2BYTEMSK(REG_COMBO_PHY0_P0_11_L, 0, BMASK(12:0)); in _mhal_mhl_HdmiBypassModeSetting()
417 W2BYTEMSK(REG_COMBO_PHY0_P0_6E_L, BIT(8), BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
426 … W2BYTEMSK(REG_COMBO_PHY0_P0_6B_L, (pMHLSignalStatus->ucImpedanceValue << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
434 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/mhl/internal/ |
| H A D | halMHL.c | 410 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
411 … W2BYTEMSK(REG_COMBO_PHY0_P0_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_HdmiBypassModeSetting()
412 W2BYTEMSK(REG_COMBO_PHY0_P0_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
413 W2BYTEMSK(REG_HDCP_DUAL_P0_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
414 W2BYTEMSK(REG_COMBO_PHY0_P0_6F_L, 0, BIT(10)); // I-control PD overwrite write in _mhal_mhl_HdmiBypassModeSetting()
415 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
416 W2BYTEMSK(REG_COMBO_PHY0_P0_11_L, 0, BMASK(12:0)); in _mhal_mhl_HdmiBypassModeSetting()
417 W2BYTEMSK(REG_COMBO_PHY0_P0_6E_L, BIT(8), BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
426 … W2BYTEMSK(REG_COMBO_PHY0_P0_6B_L, (pMHLSignalStatus->ucImpedanceValue << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
434 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/mhl/internal/ |
| H A D | halMHL.c | 410 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
411 … W2BYTEMSK(REG_COMBO_PHY0_P0_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_HdmiBypassModeSetting()
412 W2BYTEMSK(REG_COMBO_PHY0_P0_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
413 W2BYTEMSK(REG_HDCP_DUAL_P0_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
414 W2BYTEMSK(REG_COMBO_PHY0_P0_6F_L, 0, BIT(10)); // I-control PD overwrite write in _mhal_mhl_HdmiBypassModeSetting()
415 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
416 W2BYTEMSK(REG_COMBO_PHY0_P0_11_L, 0, BMASK(12:0)); in _mhal_mhl_HdmiBypassModeSetting()
417 W2BYTEMSK(REG_COMBO_PHY0_P0_6E_L, BIT(8), BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
426 … W2BYTEMSK(REG_COMBO_PHY0_P0_6B_L, (pMHLSignalStatus->ucImpedanceValue << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
434 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/mhl/internal/ |
| H A D | halMHL.c | 410 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
411 … W2BYTEMSK(REG_COMBO_PHY0_P0_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_HdmiBypassModeSetting()
412 W2BYTEMSK(REG_COMBO_PHY0_P0_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
413 W2BYTEMSK(REG_HDCP_DUAL_P0_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
414 W2BYTEMSK(REG_COMBO_PHY0_P0_6F_L, 0, BIT(10)); // I-control PD overwrite write in _mhal_mhl_HdmiBypassModeSetting()
415 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
416 W2BYTEMSK(REG_COMBO_PHY0_P0_11_L, 0, BMASK(12:0)); in _mhal_mhl_HdmiBypassModeSetting()
417 W2BYTEMSK(REG_COMBO_PHY0_P0_6E_L, BIT(8), BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
426 … W2BYTEMSK(REG_COMBO_PHY0_P0_6B_L, (pMHLSignalStatus->ucImpedanceValue << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
434 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/mhl/internal/ |
| H A D | halMHL.c | 410 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
411 … W2BYTEMSK(REG_COMBO_PHY0_P0_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_HdmiBypassModeSetting()
412 W2BYTEMSK(REG_COMBO_PHY0_P0_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
413 W2BYTEMSK(REG_HDCP_DUAL_P0_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
414 W2BYTEMSK(REG_COMBO_PHY0_P0_6F_L, 0, BIT(10)); // I-control PD overwrite write in _mhal_mhl_HdmiBypassModeSetting()
415 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
416 W2BYTEMSK(REG_COMBO_PHY0_P0_11_L, 0, BMASK(12:0)); in _mhal_mhl_HdmiBypassModeSetting()
417 W2BYTEMSK(REG_COMBO_PHY0_P0_6E_L, BIT(8), BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
426 … W2BYTEMSK(REG_COMBO_PHY0_P0_6B_L, (pMHLSignalStatus->ucImpedanceValue << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
434 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_hdmi.c | 320 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
321 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(1), BIT(1)); in _Hal_tmds_GetClockValidFlag()
331 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
332 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(2), BIT(2)); in _Hal_tmds_GetClockValidFlag()
342 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
343 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(3), BIT(3)); in _Hal_tmds_GetClockValidFlag()
353 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
354 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(4), BIT(4)); in _Hal_tmds_GetClockValidFlag()
474 W2BYTEMSK(REG_PM_SCDC0_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
475 W2BYTEMSK(REG_PM_SCDC0_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_hdmi.c | 300 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
301 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(1), BIT(1)); in _Hal_tmds_GetClockValidFlag()
311 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
312 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(2), BIT(2)); in _Hal_tmds_GetClockValidFlag()
322 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
323 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(3), BIT(3)); in _Hal_tmds_GetClockValidFlag()
333 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
334 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(4), BIT(4)); in _Hal_tmds_GetClockValidFlag()
402 W2BYTEMSK(REG_PM_SCDC0_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
403 W2BYTEMSK(REG_PM_SCDC0_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_hdmi.c | 303 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
304 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(1), BIT(1)); in _Hal_tmds_GetClockValidFlag()
314 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
315 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(2), BIT(2)); in _Hal_tmds_GetClockValidFlag()
325 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
326 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(3), BIT(3)); in _Hal_tmds_GetClockValidFlag()
336 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
337 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(4), BIT(4)); in _Hal_tmds_GetClockValidFlag()
405 W2BYTEMSK(REG_PM_SCDC0_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
406 W2BYTEMSK(REG_PM_SCDC0_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_hdmi.c | 303 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
304 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(1), BIT(1)); in _Hal_tmds_GetClockValidFlag()
314 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
315 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(2), BIT(2)); in _Hal_tmds_GetClockValidFlag()
325 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
326 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(3), BIT(3)); in _Hal_tmds_GetClockValidFlag()
336 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
337 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(4), BIT(4)); in _Hal_tmds_GetClockValidFlag()
405 W2BYTEMSK(REG_PM_SCDC0_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
406 W2BYTEMSK(REG_PM_SCDC0_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_hdmi.c | 386 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
387 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(1), BIT(1)); in _Hal_tmds_GetClockValidFlag()
397 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
398 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(2), BIT(2)); in _Hal_tmds_GetClockValidFlag()
408 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
409 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(3), BIT(3)); in _Hal_tmds_GetClockValidFlag()
419 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
420 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(4), BIT(4)); in _Hal_tmds_GetClockValidFlag()
540 W2BYTEMSK(REG_PM_SCDC0_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
541 W2BYTEMSK(REG_PM_SCDC0_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_hdmi.c | 386 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
387 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(1), BIT(1)); in _Hal_tmds_GetClockValidFlag()
397 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
398 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(2), BIT(2)); in _Hal_tmds_GetClockValidFlag()
408 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
409 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(3), BIT(3)); in _Hal_tmds_GetClockValidFlag()
419 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
420 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(4), BIT(4)); in _Hal_tmds_GetClockValidFlag()
540 W2BYTEMSK(REG_PM_SCDC0_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
541 W2BYTEMSK(REG_PM_SCDC0_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_hdmi.c | 307 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
308 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(1), BIT(1)); in _Hal_tmds_GetClockValidFlag()
318 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
319 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(2), BIT(2)); in _Hal_tmds_GetClockValidFlag()
329 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
330 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(3), BIT(3)); in _Hal_tmds_GetClockValidFlag()
340 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
341 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(4), BIT(4)); in _Hal_tmds_GetClockValidFlag()
410 W2BYTEMSK(REG_PM_SCDC0_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
411 W2BYTEMSK(REG_PM_SCDC0_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_hdmi.c | 307 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
308 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(1), BIT(1)); in _Hal_tmds_GetClockValidFlag()
318 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
319 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(2), BIT(2)); in _Hal_tmds_GetClockValidFlag()
329 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
330 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(3), BIT(3)); in _Hal_tmds_GetClockValidFlag()
340 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
341 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(4), BIT(4)); in _Hal_tmds_GetClockValidFlag()
410 W2BYTEMSK(REG_PM_SCDC0_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
411 W2BYTEMSK(REG_PM_SCDC0_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_hdmi.c | 303 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
304 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(1), BIT(1)); in _Hal_tmds_GetClockValidFlag()
314 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
315 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(2), BIT(2)); in _Hal_tmds_GetClockValidFlag()
325 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
326 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(3), BIT(3)); in _Hal_tmds_GetClockValidFlag()
336 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
337 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(4), BIT(4)); in _Hal_tmds_GetClockValidFlag()
405 W2BYTEMSK(REG_PM_SCDC0_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
406 W2BYTEMSK(REG_PM_SCDC0_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_hdmi.c | 326 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
327 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(1), BIT(1)); in _Hal_tmds_GetClockValidFlag()
337 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
338 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(2), BIT(2)); in _Hal_tmds_GetClockValidFlag()
348 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
349 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(3), BIT(3)); in _Hal_tmds_GetClockValidFlag()
359 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
360 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(4), BIT(4)); in _Hal_tmds_GetClockValidFlag()
481 W2BYTEMSK(REG_PM_SCDC0_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
482 W2BYTEMSK(REG_PM_SCDC0_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_hdmi.c | 326 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
327 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(1), BIT(1)); in _Hal_tmds_GetClockValidFlag()
337 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
338 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(2), BIT(2)); in _Hal_tmds_GetClockValidFlag()
348 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
349 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(3), BIT(3)); in _Hal_tmds_GetClockValidFlag()
359 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
360 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(4), BIT(4)); in _Hal_tmds_GetClockValidFlag()
481 W2BYTEMSK(REG_PM_SCDC0_0C_L, BMASK(3:2), BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
482 W2BYTEMSK(REG_PM_SCDC0_0C_L, 0, BMASK(3:2)); in _Hal_tmds_ResetHDMI20VersionFlag()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/mhl/internal/ |
| H A D | halMHL.c | 269 W2BYTEMSK(REG_DVI_DTOP_00_L, BIT(4), BIT(4)); // enable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
270 W2BYTEMSK(REG_DVI_DTOP_2F_L, BIT(0), BIT(0)); // enable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
274 W2BYTEMSK(REG_DVI_DTOP_00_L, 0, BIT(4)); // disable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
275 W2BYTEMSK(REG_DVI_DTOP_2F_L, 0, BIT(0)); // disable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
299 W2BYTEMSK(REG_DVI_DTOP1_00_L, BIT(4), BIT(4)); // enable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
300 W2BYTEMSK(REG_DVI_DTOP1_2F_L, BIT(0), BIT(0)); // enable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
304 W2BYTEMSK(REG_DVI_DTOP1_00_L, 0, BIT(4)); // disable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
305 W2BYTEMSK(REG_DVI_DTOP1_2F_L, 0, BIT(0)); // disable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
329 W2BYTEMSK(REG_DVI_DTOP3_00_L, BIT(4), BIT(4)); // enable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
330 W2BYTEMSK(REG_DVI_DTOP3_2F_L, BIT(0), BIT(0)); // enable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/mhl/internal/ |
| H A D | halMHL.c | 269 W2BYTEMSK(REG_DVI_DTOP_00_L, BIT(4), BIT(4)); // enable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
270 W2BYTEMSK(REG_DVI_DTOP_2F_L, BIT(0), BIT(0)); // enable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
274 W2BYTEMSK(REG_DVI_DTOP_00_L, 0, BIT(4)); // disable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
275 W2BYTEMSK(REG_DVI_DTOP_2F_L, 0, BIT(0)); // disable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
299 W2BYTEMSK(REG_DVI_DTOP1_00_L, BIT(4), BIT(4)); // enable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
300 W2BYTEMSK(REG_DVI_DTOP1_2F_L, BIT(0), BIT(0)); // enable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
304 W2BYTEMSK(REG_DVI_DTOP1_00_L, 0, BIT(4)); // disable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
305 W2BYTEMSK(REG_DVI_DTOP1_2F_L, 0, BIT(0)); // disable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
329 W2BYTEMSK(REG_DVI_DTOP3_00_L, BIT(4), BIT(4)); // enable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
330 W2BYTEMSK(REG_DVI_DTOP3_2F_L, BIT(0), BIT(0)); // enable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/mhl/internal/ |
| H A D | halMHL.c | 409 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
410 … W2BYTEMSK(REG_COMBO_PHY0_P0_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_HdmiBypassModeSetting()
411 W2BYTEMSK(REG_COMBO_PHY0_P0_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
412 W2BYTEMSK(REG_HDCP_DUAL_P0_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
413 W2BYTEMSK(REG_COMBO_PHY0_P0_6F_L, 0, BIT(10)); // I-control PD overwrite write in _mhal_mhl_HdmiBypassModeSetting()
414 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
415 W2BYTEMSK(REG_COMBO_PHY0_P0_11_L, 0, BMASK(12:0)); in _mhal_mhl_HdmiBypassModeSetting()
416 W2BYTEMSK(REG_COMBO_PHY0_P0_6E_L, BIT(8), BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
420 W2BYTEMSK(REG_COMBO_PHY0_P0_59_L, 0, BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
421 W2BYTEMSK(REG_COMBO_PHY0_P0_6B_L, (MHL_IMPEDANCE_VALUE << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/mhl/internal/ |
| H A D | halMHL.c | 409 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
410 … W2BYTEMSK(REG_COMBO_PHY0_P0_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_HdmiBypassModeSetting()
411 W2BYTEMSK(REG_COMBO_PHY0_P0_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
412 W2BYTEMSK(REG_HDCP_DUAL_P0_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
413 W2BYTEMSK(REG_COMBO_PHY0_P0_6F_L, 0, BIT(10)); // I-control PD overwrite write in _mhal_mhl_HdmiBypassModeSetting()
414 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
418 W2BYTEMSK(REG_COMBO_PHY0_P0_59_L, 0, BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
419 W2BYTEMSK(REG_COMBO_PHY0_P0_6B_L, (MHL_IMPEDANCE_VALUE << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
430 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
431 … W2BYTEMSK(REG_COMBO_PHY0_P1_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_HdmiBypassModeSetting()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/ |
| H A D | mhal_mux.c | 216 W2BYTEMSK( REG_DVI_PS_0B_L, 0, BIT(10)); in Hal_SC_mux_set_dvi_mux()
217 W2BYTEMSK( REG_DVI_PS1_0B_L, 0, BIT(10)); in Hal_SC_mux_set_dvi_mux()
218 W2BYTEMSK( REG_DVI_PS2_0B_L, 0, BIT(10)); in Hal_SC_mux_set_dvi_mux()
219 W2BYTEMSK( REG_DVI_PS3_0B_L, 0, BIT(10)); in Hal_SC_mux_set_dvi_mux()
229 … W2BYTEMSK( REG_DVI_DTOP_29_L, 0xE300, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
230 …W2BYTEMSK( REG_DVI_DTOP_2A_L, 0xE3E3, HBMASK|LBMASK); // [15:8]: update Rch slowly, [7:0]:update G… in Hal_SC_mux_set_dvi_mux()
233 … W2BYTEMSK( REG_DVI_DTOP_29_L, 0, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
236 W2BYTEMSK( REG_DVI_DTOP1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
237 …W2BYTEMSK( REG_DVI_DTOP1_2A_L, 0, BIT(15)|BIT(7)); // [15]: turn off slowly updated, [7]: turn off… in Hal_SC_mux_set_dvi_mux()
238 W2BYTEMSK( REG_DVI_DTOP2_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
[all …]
|
| H A D | mhal_hdmi.c | 257 …W2BYTEMSK(REG_HDCP_19_L + dwBKOffset, BIT(15)|BIT(1), BIT(15)|BIT(1)); //[15]: Enable CPU write; [… in Hal_HDCP22_PortInit()
258 W2BYTEMSK(REG_HDCP_00_L + dwBKOffset, 0, BIT(1)); //[1]: disable SRAM read in Hal_HDCP22_PortInit()
261 W2BYTEMSK(REG_HDCP_17_L + dwBKOffset, BIT(10), BIT(10)); //HDCP enable for DDC in Hal_HDCP22_PortInit()
262 W2BYTEMSK(REG_HDCP_19_L + dwBKOffset, BIT(15), BMASK(15:14)); //write enable in Hal_HDCP22_PortInit()
264 W2BYTEMSK(REG_HDCP_17_L + dwBKOffset, 0x50, BMASK(9:0)); //CPU r/w address in Hal_HDCP22_PortInit()
265 W2BYTEMSK(REG_HDCP_19_L + dwBKOffset, BIT(5), BIT(5)); //HDCP load address pulse in Hal_HDCP22_PortInit()
267 W2BYTEMSK(REG_HDCP_18_L + dwBKOffset, 0x04, BMASK(7:0)); //bit2: HDCP22 version in Hal_HDCP22_PortInit()
268 W2BYTEMSK(REG_HDCP_19_L + dwBKOffset, BIT(4), BIT(4)); //HDCP data write port pulse generate in Hal_HDCP22_PortInit()
271 W2BYTEMSK(REG_HDCP22_P0_31_L + dwBKOffset22, 0x00, BMASK(9:0)); //reg_message_length in Hal_HDCP22_PortInit()
272 W2BYTEMSK(REG_HDCP22_P0_31_L + dwBKOffset22, BIT(15), BIT(15)); //reg_message_length_update in Hal_HDCP22_PortInit()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/ |
| H A D | mhal_mux.c | 216 W2BYTEMSK( REG_DVI_PS_0B_L, 0, BIT(10)); in Hal_SC_mux_set_dvi_mux()
217 W2BYTEMSK( REG_DVI_PS1_0B_L, 0, BIT(10)); in Hal_SC_mux_set_dvi_mux()
218 W2BYTEMSK( REG_DVI_PS2_0B_L, 0, BIT(10)); in Hal_SC_mux_set_dvi_mux()
219 W2BYTEMSK( REG_DVI_PS3_0B_L, 0, BIT(10)); in Hal_SC_mux_set_dvi_mux()
229 … W2BYTEMSK( REG_DVI_DTOP_29_L, 0xE300, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
230 …W2BYTEMSK( REG_DVI_DTOP_2A_L, 0xE3E3, HBMASK|LBMASK); // [15:8]: update Rch slowly, [7:0]:update G… in Hal_SC_mux_set_dvi_mux()
233 … W2BYTEMSK( REG_DVI_DTOP_29_L, 0, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
236 W2BYTEMSK( REG_DVI_DTOP1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
237 …W2BYTEMSK( REG_DVI_DTOP1_2A_L, 0, BIT(15)|BIT(7)); // [15]: turn off slowly updated, [7]: turn off… in Hal_SC_mux_set_dvi_mux()
238 W2BYTEMSK( REG_DVI_DTOP2_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
[all …]
|
| H A D | mhal_hdmi.c | 257 …W2BYTEMSK(REG_HDCP_19_L + dwBKOffset, BIT(15)|BIT(1), BIT(15)|BIT(1)); //[15]: Enable CPU write; [… in Hal_HDCP22_PortInit()
258 W2BYTEMSK(REG_HDCP_00_L + dwBKOffset, 0, BIT(1)); //[1]: disable SRAM read in Hal_HDCP22_PortInit()
261 W2BYTEMSK(REG_HDCP_17_L + dwBKOffset, BIT(10), BIT(10)); //HDCP enable for DDC in Hal_HDCP22_PortInit()
262 W2BYTEMSK(REG_HDCP_19_L + dwBKOffset, BIT(15), BMASK(15:14)); //write enable in Hal_HDCP22_PortInit()
264 W2BYTEMSK(REG_HDCP_17_L + dwBKOffset, 0x50, BMASK(9:0)); //CPU r/w address in Hal_HDCP22_PortInit()
265 W2BYTEMSK(REG_HDCP_19_L + dwBKOffset, BIT(5), BIT(5)); //HDCP load address pulse in Hal_HDCP22_PortInit()
267 W2BYTEMSK(REG_HDCP_18_L + dwBKOffset, 0x04, BMASK(7:0)); //bit2: HDCP22 version in Hal_HDCP22_PortInit()
268 W2BYTEMSK(REG_HDCP_19_L + dwBKOffset, BIT(4), BIT(4)); //HDCP data write port pulse generate in Hal_HDCP22_PortInit()
271 W2BYTEMSK(REG_HDCP22_P0_31_L + dwBKOffset22, 0x00, BMASK(9:0)); //reg_message_length in Hal_HDCP22_PortInit()
272 W2BYTEMSK(REG_HDCP22_P0_31_L + dwBKOffset22, BIT(15), BIT(15)); //reg_message_length_update in Hal_HDCP22_PortInit()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_hdmi.c | 281 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
282 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(1), BIT(1)); in _Hal_tmds_GetClockValidFlag()
319 W2BYTEMSK(REG_COMBO_PHY0_P0_5B_L, bPowerOn? 0: (BIT(13)| BMASK(3:0)), BIT(13)| BMASK(3:0)); in _Hal_tmds_PowerDownControl()
334 W2BYTEMSK(REG_COMBO_PHY0_P0_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
335 …W2BYTEMSK(REG_COMBO_PHY0_P0_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
350 W2BYTEMSK(REG_PM_SLEEP_3A_L, BMASK(7:4)| BIT(1), BMASK(7:0)); in _Hal_tmds_ClockStatusInitial()
351 W2BYTEMSK(REG_PM_SLEEP_3D_L, TMDS_CLOCK_CMP_VALUE0, BMASK(11:0)); in _Hal_tmds_ClockStatusInitial()
352 W2BYTEMSK(REG_PM_SLEEP_3E_L, TMDS_CLOCK_CMP_VALUE1, BMASK(11:0)); in _Hal_tmds_ClockStatusInitial()
353 W2BYTEMSK(REG_PM_SLEEP_00_L, 0, BIT(1)); // Clock status mask in _Hal_tmds_ClockStatusInitial()
354 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
[all …]
|