Lines Matching refs:W2BYTEMSK
269 W2BYTEMSK(REG_DVI_DTOP_00_L, BIT(4), BIT(4)); // enable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
270 W2BYTEMSK(REG_DVI_DTOP_2F_L, BIT(0), BIT(0)); // enable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
274 W2BYTEMSK(REG_DVI_DTOP_00_L, 0, BIT(4)); // disable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
275 W2BYTEMSK(REG_DVI_DTOP_2F_L, 0, BIT(0)); // disable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
299 W2BYTEMSK(REG_DVI_DTOP1_00_L, BIT(4), BIT(4)); // enable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
300 W2BYTEMSK(REG_DVI_DTOP1_2F_L, BIT(0), BIT(0)); // enable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
304 W2BYTEMSK(REG_DVI_DTOP1_00_L, 0, BIT(4)); // disable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
305 W2BYTEMSK(REG_DVI_DTOP1_2F_L, 0, BIT(0)); // disable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
329 W2BYTEMSK(REG_DVI_DTOP3_00_L, BIT(4), BIT(4)); // enable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
330 W2BYTEMSK(REG_DVI_DTOP3_2F_L, BIT(0), BIT(0)); // enable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
334 W2BYTEMSK(REG_DVI_DTOP3_00_L, 0, BIT(4)); // disable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
335 W2BYTEMSK(REG_DVI_DTOP3_2F_L, 0, BIT(0)); // disable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
359 W2BYTEMSK(REG_DVI_DTOP2_00_L, BIT(4), BIT(4)); // enable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
360 W2BYTEMSK(REG_DVI_DTOP2_2F_L, BIT(0), BIT(0)); // enable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
364 W2BYTEMSK(REG_DVI_DTOP2_00_L, 0, BIT(4)); // disable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
365 W2BYTEMSK(REG_DVI_DTOP2_2F_L, 0, BIT(0)); // disable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
397 W2BYTEMSK(REG_DVI_DTOP_27_L, 0, BMASK(2:1)); // [2:1]: MHL_SEL in _mhal_mhl_HdmiBypassModeSetting()
398 W2BYTEMSK(REG_DVI_DTOP_20_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength in _mhal_mhl_HdmiBypassModeSetting()
399 W2BYTEMSK(REG_DVI_DTOP_0E_L, BIT(4), BIT(4)); // auto clear phase accumulator in _mhal_mhl_HdmiBypassModeSetting()
400 W2BYTEMSK(REG_DVI_DTOP_3B_L, 0, BIT(4)); // overwirte enable in _mhal_mhl_HdmiBypassModeSetting()
401 W2BYTEMSK(REG_DVI_DTOP_3D_L, 0, BIT(4)); // overwirte enable in _mhal_mhl_HdmiBypassModeSetting()
402 W2BYTEMSK(REG_DVI_DTOP_3F_L, 0, BIT(4)); // overwirte enable in _mhal_mhl_HdmiBypassModeSetting()
404 W2BYTEMSK(REG_DVI_DTOP_2F_L, 0, BMASK(15:4)| BMASK(3:2)); in _mhal_mhl_HdmiBypassModeSetting()
405 …W2BYTEMSK(REG_DVI_ATOP_32_L, BIT(8), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Bypa… in _mhal_mhl_HdmiBypassModeSetting()
406 …W2BYTEMSK(REG_DVI_ATOP_38_L, 0, BIT(10) |BIT(8)); // [10]: auto acdr mode selection, [8]: enable a… in _mhal_mhl_HdmiBypassModeSetting()
407 …W2BYTEMSK(REG_DVI_ATOP_5E_L, 0, BMASK(4:0)); //[4]: overwrtie DPL ICTL value, [3:0]: ictl overwrti… in _mhal_mhl_HdmiBypassModeSetting()
408 W2BYTEMSK(REG_DVI_DTOP_0E_L, 0, BIT(4)); // auto clear phase accumulator in _mhal_mhl_HdmiBypassModeSetting()
409 W2BYTEMSK(REG_HDCP_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
413 W2BYTEMSK(REG_DVI_DTOP_0C_L, MHL_IMPEDANCE_VALUE, BIT(9)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
424 W2BYTEMSK(REG_DVI_DTOP1_27_L, 0, BMASK(2:1)); // [2:1]: MHL_SEL in _mhal_mhl_HdmiBypassModeSetting()
425 W2BYTEMSK(REG_DVI_DTOP1_20_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength in _mhal_mhl_HdmiBypassModeSetting()
426 W2BYTEMSK(REG_DVI_DTOP1_0E_L, BIT(4), BIT(4)); // auto clear phase accumulator in _mhal_mhl_HdmiBypassModeSetting()
427 W2BYTEMSK(REG_DVI_DTOP1_3B_L, 0, BIT(4)); // overwirte enable in _mhal_mhl_HdmiBypassModeSetting()
428 W2BYTEMSK(REG_DVI_DTOP1_3D_L, 0, BIT(4)); // overwirte enable in _mhal_mhl_HdmiBypassModeSetting()
429 W2BYTEMSK(REG_DVI_DTOP1_3F_L, 0, BIT(4)); // overwirte enable in _mhal_mhl_HdmiBypassModeSetting()
430 …W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(8), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Byp… in _mhal_mhl_HdmiBypassModeSetting()
431 …W2BYTEMSK(REG_DVI_ATOP1_5E_L, 0, BMASK(4:0)); //[4]: overwrtie DPL ICTL value, [3:0]: ictl overwrt… in _mhal_mhl_HdmiBypassModeSetting()
432 W2BYTEMSK(REG_DVI_ATOP1_60_L, 0, BIT(7)); // power on DVI PLL in _mhal_mhl_HdmiBypassModeSetting()
433 W2BYTEMSK(REG_DVI_DTOP1_0E_L, 0, BIT(4)); // auto clear phase accumulator in _mhal_mhl_HdmiBypassModeSetting()
434 W2BYTEMSK(REG_DVI_ATOP1_60_L, 0, BMASK(2:1)); // [2:0]: power down RD in _mhal_mhl_HdmiBypassModeSetting()
435 …W2BYTEMSK(REG_DVI_ATOP1_74_L, 0, BMASK(5:0)); // [2:0]: power down DPLPHI, [5:3]: power down DPLPHQ in _mhal_mhl_HdmiBypassModeSetting()
436 W2BYTEMSK(REG_HDCP1_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
440 W2BYTEMSK(REG_DVI_DTOP1_0C_L, MHL_IMPEDANCE_VALUE, BIT(9) |BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
451 W2BYTEMSK(REG_DVI_DTOP3_27_L, 0, BMASK(2:1)); // [2:1]: MHL_SEL in _mhal_mhl_HdmiBypassModeSetting()
452 W2BYTEMSK(REG_DVI_DTOP3_20_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength in _mhal_mhl_HdmiBypassModeSetting()
453 W2BYTEMSK(REG_DVI_DTOP3_0E_L, BIT(4), BIT(4)); // auto clear phase accumulator in _mhal_mhl_HdmiBypassModeSetting()
454 W2BYTEMSK(REG_DVI_DTOP3_3B_L, 0, BIT(4)); // overwirte enable in _mhal_mhl_HdmiBypassModeSetting()
455 W2BYTEMSK(REG_DVI_DTOP3_3D_L, 0, BIT(4)); // overwirte enable in _mhal_mhl_HdmiBypassModeSetting()
456 W2BYTEMSK(REG_DVI_DTOP3_3F_L, 0, BIT(4)); // overwirte enable in _mhal_mhl_HdmiBypassModeSetting()
458 W2BYTEMSK(REG_DVI_DTOP3_2F_L, 0, BMASK(15:4)| BMASK(3:2)); in _mhal_mhl_HdmiBypassModeSetting()
459 …W2BYTEMSK(REG_DVI_ATOP3_32_L, BIT(8), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Byp… in _mhal_mhl_HdmiBypassModeSetting()
460 …W2BYTEMSK(REG_DVI_ATOP3_35_L, 0, BIT(10) |BIT(8)); // [10]: auto acdr mode selection, [8]: enable … in _mhal_mhl_HdmiBypassModeSetting()
461 …W2BYTEMSK(REG_DVI_ATOP3_5E_L, 0, BMASK(4:0)); //[4]: overwrtie DPL ICTL value, [3:0]: ictl overwrt… in _mhal_mhl_HdmiBypassModeSetting()
462 W2BYTEMSK(REG_DVI_DTOP3_0E_L, 0, BIT(4)); // auto clear phase accumulator in _mhal_mhl_HdmiBypassModeSetting()
463 W2BYTEMSK(REG_HDCP3_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
467 W2BYTEMSK(REG_DVI_DTOP3_0C_L, MHL_IMPEDANCE_VALUE, BIT(9)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
478 …W2BYTEMSK(REG_DVI_DTOP2_27_L, 0x2C6C, BMASK(14:0)); // [7]: MHL HW mode, [1]: MHL pack-pixel mode,… in _mhal_mhl_HdmiBypassModeSetting()
479 W2BYTEMSK(REG_DVI_DTOP2_20_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength in _mhal_mhl_HdmiBypassModeSetting()
480 W2BYTEMSK(REG_DVI_DTOP2_0E_L, BIT(4), BIT(4)); // auto clear phase accumulator in _mhal_mhl_HdmiBypassModeSetting()
481 W2BYTEMSK(REG_DVI_DTOP2_3B_L, 0, BIT(4)); // overwirte enable in _mhal_mhl_HdmiBypassModeSetting()
482 W2BYTEMSK(REG_DVI_DTOP2_3D_L, 0, BIT(4)); // overwirte enable in _mhal_mhl_HdmiBypassModeSetting()
483 W2BYTEMSK(REG_DVI_DTOP2_3F_L, 0, BIT(4)); // overwirte enable in _mhal_mhl_HdmiBypassModeSetting()
485 W2BYTEMSK(REG_DVI_DTOP2_2F_L, 0, BMASK(15:4)| BMASK(3:2)); in _mhal_mhl_HdmiBypassModeSetting()
486 …W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(8), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Byp… in _mhal_mhl_HdmiBypassModeSetting()
487 …W2BYTEMSK(REG_DVI_ATOP2_35_L, 0, BIT(10) |BIT(8)); // [10]: auto acdr mode selection, [8]: enable … in _mhal_mhl_HdmiBypassModeSetting()
488 …W2BYTEMSK(REG_DVI_ATOP2_5E_L, 0, BMASK(4:0)); //[4]: overwrtie DPL ICTL value, [3:0]: ictl overwrt… in _mhal_mhl_HdmiBypassModeSetting()
489 W2BYTEMSK(REG_DVI_DTOP2_0E_L, 0, BIT(4)); // auto clear phase accumulator in _mhal_mhl_HdmiBypassModeSetting()
490 W2BYTEMSK(REG_HDCP2_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
494 W2BYTEMSK(REG_DVI_DTOP2_0C_L, MHL_IMPEDANCE_VALUE, BIT(9) |BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
527 W2BYTEMSK(REG_DVI_DTOP_27_L, BIT(2), BMASK(2:1)); // [2:1]: MHL_SEL in _mhal_mhl_Mhl24bitsModeSetting()
528 W2BYTEMSK(REG_DVI_DTOP_20_L, MHL_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength in _mhal_mhl_Mhl24bitsModeSetting()
529 W2BYTEMSK(REG_DVI_DTOP_0E_L, 0, BIT(4)); // auto clear phase accumulator in _mhal_mhl_Mhl24bitsModeSetting()
530 W2BYTEMSK(REG_DVI_DTOP_3A_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
531 W2BYTEMSK(REG_DVI_DTOP_3B_L, BIT(4), BIT(4)); // overwirte enable in _mhal_mhl_Mhl24bitsModeSetting()
532 W2BYTEMSK(REG_DVI_DTOP_3C_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
533 W2BYTEMSK(REG_DVI_DTOP_3D_L, BIT(4), BIT(4)); // overwirte enable in _mhal_mhl_Mhl24bitsModeSetting()
534 W2BYTEMSK(REG_DVI_DTOP_3E_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
535 W2BYTEMSK(REG_DVI_DTOP_3F_L, BIT(4), BIT(4)); // overwirte enable in _mhal_mhl_Mhl24bitsModeSetting()
537 …W2BYTEMSK(REG_DVI_DTOP_2F_L, (MHL_DIGITAL_UNLOCK_RANGE << 4)| BMASK(3:2), BMASK(15:4)| BMASK(3:2)); in _mhal_mhl_Mhl24bitsModeSetting()
538 …W2BYTEMSK(REG_DVI_ATOP_32_L, BIT(8) |BIT(4) |BIT(0), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, E… in _mhal_mhl_Mhl24bitsModeSetting()
539 …W2BYTEMSK(REG_DVI_ATOP_38_L, BIT(10) |BIT(8), BIT(10) |BIT(8)); // [10]: auto acdr mode selection,… in _mhal_mhl_Mhl24bitsModeSetting()
540 …W2BYTEMSK(REG_DVI_ATOP_5E_L, BIT(4)| ucIControlValue, BMASK(4:0)); //[4]: overwrtie DPL ICTL value… in _mhal_mhl_Mhl24bitsModeSetting()
541 W2BYTEMSK(REG_HDCP_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_Mhl24bitsModeSetting()
545 W2BYTEMSK(REG_DVI_DTOP_0C_L, BIT(9)| ucImpedanceValue, BIT(9)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
556 W2BYTEMSK(REG_DVI_DTOP1_27_L, BIT(2), BMASK(2:1)); // [2:1]: MHL_SEL in _mhal_mhl_Mhl24bitsModeSetting()
557 W2BYTEMSK(REG_DVI_DTOP1_20_L, MHL_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength in _mhal_mhl_Mhl24bitsModeSetting()
558 W2BYTEMSK(REG_DVI_DTOP1_0E_L, 0, BIT(4)); // auto clear phase accumulator in _mhal_mhl_Mhl24bitsModeSetting()
559 W2BYTEMSK(REG_DVI_DTOP1_3A_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
560 W2BYTEMSK(REG_DVI_DTOP1_3B_L, BIT(4), BIT(4)); // overwirte enable in _mhal_mhl_Mhl24bitsModeSetting()
561 W2BYTEMSK(REG_DVI_DTOP1_3C_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
562 W2BYTEMSK(REG_DVI_DTOP1_3D_L, BIT(4), BIT(4)); // overwirte enable in _mhal_mhl_Mhl24bitsModeSetting()
563 W2BYTEMSK(REG_DVI_DTOP1_3E_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
564 W2BYTEMSK(REG_DVI_DTOP1_3F_L, BIT(4), BIT(4)); // overwirte enable in _mhal_mhl_Mhl24bitsModeSetting()
565 …W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(8) |BIT(4) |BIT(0), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, … in _mhal_mhl_Mhl24bitsModeSetting()
566 …W2BYTEMSK(REG_DVI_ATOP1_5E_L, BIT(4) |ucIControlValue, BMASK(4:0)); // enable to overwrtie DPL ICT… in _mhal_mhl_Mhl24bitsModeSetting()
567 W2BYTEMSK(REG_DVI_ATOP1_60_L, BMASK(2:1), BMASK(2:1)); // [2:0]: power down RD in _mhal_mhl_Mhl24bitsModeSetting()
568 …W2BYTEMSK(REG_DVI_ATOP1_74_L, BMASK(5:0), BMASK(5:0)); // [2:0]: power down DPLPHI, [5:3]: power d… in _mhal_mhl_Mhl24bitsModeSetting()
569 W2BYTEMSK(REG_HDCP1_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_Mhl24bitsModeSetting()
573 W2BYTEMSK(REG_DVI_DTOP1_0C_L, BIT(9)| ucImpedanceValue, BIT(9)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
584 …W2BYTEMSK(REG_DVI_DTOP3_27_L, BIT(2), BMASK(2:1)); // [7]: MHL HW mode, [1]: MHL pack-pixel mode, … in _mhal_mhl_Mhl24bitsModeSetting()
585 W2BYTEMSK(REG_DVI_DTOP3_20_L, MHL_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength in _mhal_mhl_Mhl24bitsModeSetting()
586 W2BYTEMSK(REG_DVI_DTOP3_0E_L, 0, BIT(4)); // auto clear phase accumulator in _mhal_mhl_Mhl24bitsModeSetting()
587 W2BYTEMSK(REG_DVI_DTOP3_3A_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
588 W2BYTEMSK(REG_DVI_DTOP3_3B_L, BIT(4), BIT(4)); // overwirte enable in _mhal_mhl_Mhl24bitsModeSetting()
589 W2BYTEMSK(REG_DVI_DTOP3_3C_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
590 W2BYTEMSK(REG_DVI_DTOP3_3D_L, BIT(4), BIT(4)); // overwirte enable in _mhal_mhl_Mhl24bitsModeSetting()
591 W2BYTEMSK(REG_DVI_DTOP3_3E_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
592 W2BYTEMSK(REG_DVI_DTOP3_3F_L, BIT(4), BIT(4)); // overwirte enable in _mhal_mhl_Mhl24bitsModeSetting()
594 …W2BYTEMSK(REG_DVI_DTOP3_2F_L, (MHL_DIGITAL_UNLOCK_RANGE << 4)| BMASK(3:2), BMASK(15:4)| BMASK(3:2)… in _mhal_mhl_Mhl24bitsModeSetting()
595 …W2BYTEMSK(REG_DVI_ATOP3_32_L, BIT(8) |BIT(4) |BIT(0), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, … in _mhal_mhl_Mhl24bitsModeSetting()
596 …W2BYTEMSK(REG_DVI_ATOP3_35_L, BIT(10) |BIT(8), BIT(10) |BIT(8)); // [10]: auto acdr mode selection… in _mhal_mhl_Mhl24bitsModeSetting()
597 …W2BYTEMSK(REG_DVI_ATOP3_5E_L, BIT(4)| ucIControlValue, BMASK(4:0)); //[4]: overwrtie DPL ICTL valu… in _mhal_mhl_Mhl24bitsModeSetting()
598 W2BYTEMSK(REG_HDCP3_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_Mhl24bitsModeSetting()
602 W2BYTEMSK(REG_DVI_DTOP3_0C_L, BIT(9)| ucImpedanceValue, BIT(9)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
613 …W2BYTEMSK(REG_DVI_DTOP2_27_L, BIT(2), BMASK(2:1)); // [7]: MHL HW mode, [1]: MHL pack-pixel mode, … in _mhal_mhl_Mhl24bitsModeSetting()
614 W2BYTEMSK(REG_DVI_DTOP2_20_L, MHL_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength in _mhal_mhl_Mhl24bitsModeSetting()
615 W2BYTEMSK(REG_DVI_DTOP2_0E_L, 0, BIT(4)); // auto clear phase accumulator in _mhal_mhl_Mhl24bitsModeSetting()
616 W2BYTEMSK(REG_DVI_DTOP2_3A_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
617 W2BYTEMSK(REG_DVI_DTOP2_3B_L, BIT(4), BIT(4)); // overwirte enable in _mhal_mhl_Mhl24bitsModeSetting()
618 W2BYTEMSK(REG_DVI_DTOP2_3C_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
619 W2BYTEMSK(REG_DVI_DTOP2_3D_L, BIT(4), BIT(4)); // overwirte enable in _mhal_mhl_Mhl24bitsModeSetting()
620 W2BYTEMSK(REG_DVI_DTOP2_3E_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
621 W2BYTEMSK(REG_DVI_DTOP2_3F_L, BIT(4), BIT(4)); // overwirte enable in _mhal_mhl_Mhl24bitsModeSetting()
623 …W2BYTEMSK(REG_DVI_DTOP2_2F_L, (MHL_DIGITAL_UNLOCK_RANGE << 4)| BMASK(3:2), BMASK(15:4)| BMASK(3:2)… in _mhal_mhl_Mhl24bitsModeSetting()
624 …W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(8) |BIT(4) |BIT(0), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, … in _mhal_mhl_Mhl24bitsModeSetting()
625 …W2BYTEMSK(REG_DVI_ATOP2_35_L, BIT(10) |BIT(8), BIT(10) |BIT(8)); // [10]: auto acdr mode selection… in _mhal_mhl_Mhl24bitsModeSetting()
626 …W2BYTEMSK(REG_DVI_ATOP2_5E_L, BIT(4) |ucIControlValue, BMASK(4:0)); // enable to overwrtie DPL ICT… in _mhal_mhl_Mhl24bitsModeSetting()
627 W2BYTEMSK(REG_HDCP2_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_Mhl24bitsModeSetting()
631 W2BYTEMSK(REG_DVI_DTOP2_0C_L, BIT(9)| ucImpedanceValue, BIT(9)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
664 W2BYTEMSK(REG_DVI_DTOP_27_L, BMASK(2:1), BMASK(2:1)); // [2:1]: MHL_SEL in _mhal_mhl_MhlPackedPixelModeSetting()
665 W2BYTEMSK(REG_DVI_ATOP_32_L, BMASK(9:8), BMASK(9:8)); // HF in _mhal_mhl_MhlPackedPixelModeSetting()
666 W2BYTEMSK(REG_HDCP_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_MhlPackedPixelModeSetting()
676 W2BYTEMSK(REG_DVI_DTOP1_27_L, BMASK(2:1), BMASK(2:1)); // [2:1]: MHL_SEL in _mhal_mhl_MhlPackedPixelModeSetting()
677 W2BYTEMSK(REG_DVI_ATOP1_32_L, BMASK(9:8), BMASK(9:8)); // HF in _mhal_mhl_MhlPackedPixelModeSetting()
678 W2BYTEMSK(REG_HDCP1_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_MhlPackedPixelModeSetting()
688 W2BYTEMSK(REG_DVI_DTOP3_27_L, BMASK(2:1), BMASK(2:1)); // [2:1]: MHL_SEL in _mhal_mhl_MhlPackedPixelModeSetting()
689 W2BYTEMSK(REG_DVI_ATOP3_32_L, BMASK(9:8), BMASK(9:8)); // HF in _mhal_mhl_MhlPackedPixelModeSetting()
690 W2BYTEMSK(REG_HDCP3_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_MhlPackedPixelModeSetting()
700 W2BYTEMSK(REG_DVI_DTOP2_27_L, BMASK(2:1), BMASK(2:1)); // [2:1]: MHL_SEL in _mhal_mhl_MhlPackedPixelModeSetting()
701 W2BYTEMSK(REG_DVI_ATOP2_32_L, BMASK(9:8), BMASK(9:8)); // HF in _mhal_mhl_MhlPackedPixelModeSetting()
702 W2BYTEMSK(REG_HDCP2_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_MhlPackedPixelModeSetting()
734 W2BYTEMSK(REG_DVI_ATOP_60_L, 0, BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
735 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(8));// clock R-term in _mhal_mhl_RxRtermControl()
739 W2BYTEMSK(REG_DVI_ATOP_60_L, BMASK(13:12), BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
740 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(8));// clock R-term in _mhal_mhl_RxRtermControl()
744 W2BYTEMSK(REG_DVI_ATOP_60_L, BMASK(13:11), BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
745 W2BYTEMSK(REG_PM_SLEEP_4B_L, BIT(8), BIT(8));// clock R-term in _mhal_mhl_RxRtermControl()
758 W2BYTEMSK(REG_DVI_ATOP1_60_L, 0, BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
759 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(9));// clock R-term in _mhal_mhl_RxRtermControl()
763 W2BYTEMSK(REG_DVI_ATOP1_60_L, BMASK(13:12), BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
764 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(9));// clock R-term in _mhal_mhl_RxRtermControl()
768 W2BYTEMSK(REG_DVI_ATOP1_60_L, BMASK(13:11), BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
769 W2BYTEMSK(REG_PM_SLEEP_4B_L, BIT(9), BIT(9));// clock R-term in _mhal_mhl_RxRtermControl()
782 W2BYTEMSK(REG_DVI_ATOP3_60_L, 0, BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
783 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(11));// clock R-term in _mhal_mhl_RxRtermControl()
787 W2BYTEMSK(REG_DVI_ATOP3_60_L, BMASK(13:12), BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
788 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(11));// clock R-term in _mhal_mhl_RxRtermControl()
792 W2BYTEMSK(REG_DVI_ATOP3_60_L, BMASK(13:11), BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
793 W2BYTEMSK(REG_PM_SLEEP_4B_L, BIT(11), BIT(11));// clock R-term in _mhal_mhl_RxRtermControl()
806 W2BYTEMSK(REG_DVI_ATOP2_60_L, 0, BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
807 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(10));// clock R-term in _mhal_mhl_RxRtermControl()
811 W2BYTEMSK(REG_DVI_ATOP2_60_L, BMASK(13:12), BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
812 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(10));// clock R-term in _mhal_mhl_RxRtermControl()
816 W2BYTEMSK(REG_DVI_ATOP2_60_L, BMASK(13:11), BMASK(13:11));// data R-term in _mhal_mhl_RxRtermControl()
817 W2BYTEMSK(REG_PM_SLEEP_4B_L, BIT(10), BIT(10));// clock R-term in _mhal_mhl_RxRtermControl()
842 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in _mhal_mhl_CbusForceToStandby()
843 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(15), BIT(15)); // force enter PM mode in _mhal_mhl_CbusForceToStandby()
858 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(14), BIT(14)); in _mhal_mhl_MHLForceToAttach()
880 W2BYTEMSK(REG_DVI_DTOP_27_L, bflag ?0 :BIT(0), BIT(0)); // [0]: MHL enable in _mhal_mhl_AdjustCommonModeResistor()
890 W2BYTEMSK(REG_DVI_DTOP1_27_L, bflag ?0 :BIT(0), BIT(0)); // [0]: MHL enable in _mhal_mhl_AdjustCommonModeResistor()
900 W2BYTEMSK(REG_DVI_DTOP3_27_L, bflag ?0 :BIT(0), BIT(0)); // [0]: MHL enable in _mhal_mhl_AdjustCommonModeResistor()
910 W2BYTEMSK(REG_DVI_DTOP2_27_L, bflag ?0 :BIT(0), BIT(0)); // [0]: MHL enable in _mhal_mhl_AdjustCommonModeResistor()
948 W2BYTEMSK(REG_DVI_ATOP_71_L, BIT(8), BIT(8)); in _mhal_mhl_ClockBigChangeFlag()
949 W2BYTEMSK(REG_DVI_ATOP_71_L, 0, BIT(8)); in _mhal_mhl_ClockBigChangeFlag()
964 W2BYTEMSK(REG_DVI_ATOP1_71_L, BIT(8), BIT(8)); in _mhal_mhl_ClockBigChangeFlag()
965 W2BYTEMSK(REG_DVI_ATOP1_71_L, 0, BIT(8)); in _mhal_mhl_ClockBigChangeFlag()
980 W2BYTEMSK(REG_DVI_ATOP3_71_L, BIT(8), BIT(8)); in _mhal_mhl_ClockBigChangeFlag()
981 W2BYTEMSK(REG_DVI_ATOP3_71_L, 0, BIT(8)); in _mhal_mhl_ClockBigChangeFlag()
996 W2BYTEMSK(REG_DVI_ATOP2_71_L, BIT(8), BIT(8)); in _mhal_mhl_ClockBigChangeFlag()
997 W2BYTEMSK(REG_DVI_ATOP2_71_L, 0, BIT(8)); in _mhal_mhl_ClockBigChangeFlag()
1135 W2BYTEMSK(REG_DVI_ATOP_7F_L, bFlag ?BIT(14) :0, BIT(14)); in _mhal_mhl_RtermHWControl()
1155 W2BYTEMSK(REG_DVI_ATOP3_01_L, bFlag ?BIT(0) :0, BIT(0)); in _mhal_mhl_RtermHWControl()
1165 W2BYTEMSK(REG_DVI_ATOP2_00_L, bFlag ?BIT(0) :0, BIT(0)); in _mhal_mhl_RtermHWControl()
1195 W2BYTEMSK(0x102E02, (MHL_SCALER_MUX_SELECT_MHL << 4), BMASK(7:4)); in _mhal_mhl_ChangeScalerMainMux()
1202 W2BYTEMSK(0x102E02, (MHL_SCALER_MUX_SELECT_DVI << 4), BMASK(7:4)); in _mhal_mhl_ChangeScalerMainMux()
1219 …W2BYTEMSK(REG_HDMI2_08_L, bMHLPath ?BIT(0) :0, BIT(0)); // [0]: audio source selection, 0: HDMI / … in _mhal_mhl_AudioPathSelect()
1246 W2BYTEMSK(REG_PM_SLEEP_73_L, BIT(0), BIT(6)| BIT(8)| BIT(0)); // [0]: reg_hplugc_mhl_en in _mhal_mhl_CbusAndClockSelect()
1251 W2BYTEMSK(REG_PM_SLEEP_73_L, BIT(8), BIT(14)| BIT(8)| BIT(0)); // [8]: reg_hpluga_mhl_en in _mhal_mhl_CbusAndClockSelect()
1255 W2BYTEMSK(REG_DVI_ATOP_6A_L, (ucClockSelect << 2), BMASK(3:2)); // [3:2]: HDCP clock select in _mhal_mhl_CbusAndClockSelect()
1276 … W2BYTEMSK(REG_DVI_DTOP_27_L, BIT(15), BIT(15)); // [15]: Enable MHL packed-pixel mode criteria in _mhal_mhl_PhyInitialSetting()
1277 W2BYTEMSK(REG_DVI_DTOP_28_L, BIT(0), BIT(0)); // [0]: MHL v1.2 in _mhal_mhl_PhyInitialSetting()
1297 … W2BYTEMSK(REG_DVI_DTOP3_27_L, BIT(15), BIT(15)); // [15]: Enable MHL packed-pixel mode criteria in _mhal_mhl_PhyInitialSetting()
1298 W2BYTEMSK(REG_DVI_DTOP3_28_L, BIT(0), BIT(0)); // [0]: MHL v1.2 in _mhal_mhl_PhyInitialSetting()
1308 … W2BYTEMSK(REG_DVI_DTOP2_27_L, BIT(15), BIT(15)); // [15]: Enable MHL packed-pixel mode criteria in _mhal_mhl_PhyInitialSetting()
1309 W2BYTEMSK(REG_DVI_DTOP2_28_L, BIT(0), BIT(0)); // [0]: MHL v1.2 in _mhal_mhl_PhyInitialSetting()
1649 W2BYTEMSK(REG_DVI_DTOP_0E_L, BIT(4), BIT(4)); // clear accumulator in mhal_mhl_Accumulator_Clr()
1650 W2BYTEMSK(REG_DVI_DTOP_0E_L, 0, BIT(4)); in mhal_mhl_Accumulator_Clr()
1668 W2BYTEMSK(REG_DVI_DTOP1_0E_L, BIT(4), BIT(4)); // clear accumulator in mhal_mhl_Accumulator_Clr()
1669 W2BYTEMSK(REG_DVI_DTOP1_0E_L, 0, BIT(4)); in mhal_mhl_Accumulator_Clr()
1687 W2BYTEMSK(REG_DVI_DTOP3_0E_L, BIT(4), BIT(4)); // clear accumulator in mhal_mhl_Accumulator_Clr()
1688 W2BYTEMSK(REG_DVI_DTOP3_0E_L, 0, BIT(4)); in mhal_mhl_Accumulator_Clr()
1706 W2BYTEMSK(REG_DVI_DTOP2_0E_L, BIT(4), BIT(4)); // clear accumulator in mhal_mhl_Accumulator_Clr()
1707 W2BYTEMSK(REG_DVI_DTOP2_0E_L, 0, BIT(4)); in mhal_mhl_Accumulator_Clr()
1754 W2BYTEMSK(REG_HDMI2_06_L, BIT(12), BIT(12)); in mhal_mhl_CDRModeMonitor()
1755 W2BYTEMSK(REG_HDMI2_06_L, 0, BIT(12)); in mhal_mhl_CDRModeMonitor()
1811 W2BYTEMSK(REG_HDMI2_06_L, BIT(12), BIT(12)); in mhal_mhl_CDRModeMonitor()
1812 W2BYTEMSK(REG_HDMI2_06_L, 0, BIT(12)); in mhal_mhl_CDRModeMonitor()
1858 W2BYTEMSK(REG_HDMI2_06_L, BIT(12), BIT(12)); in mhal_mhl_CDRModeMonitor()
1859 W2BYTEMSK(REG_HDMI2_06_L, 0, BIT(12)); in mhal_mhl_CDRModeMonitor()
1927 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
1931 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
1954 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
1958 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
1971 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
1975 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
2008 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0)); in mhal_mhl_VbusCharge()
2012 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
2016 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0)); in mhal_mhl_VbusCharge()
2039 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0)); in mhal_mhl_VbusCharge()
2043 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
2047 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0)); in mhal_mhl_VbusCharge()
2060 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0)); in mhal_mhl_VbusCharge()
2064 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
2068 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0)); in mhal_mhl_VbusCharge()
2095 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(5), BIT(5)); in mhal_mhl_CbusFloating()
2099 W2BYTEMSK(REG_PM_MHL_CBUS_17, 0, BIT(5)); in mhal_mhl_CbusFloating()
2117 W2BYTEMSK(REG_PM_MHL_CBUS_18, 0, BIT(1)); // cbus stuck to low int mask in mhal_mhl_CbusStucktoLow()
2121 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(1), BIT(1)); // cbus stuck to low int mask in mhal_mhl_CbusStucktoLow()
2124 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(0), BIT(0)); // Clear cbus stuck to low int flag in mhal_mhl_CbusStucktoLow()
2141 W2BYTEMSK(REG_PM_MHL_CBUS_18, 0, BIT(5)); // wake up pulse int mask in mhal_mhl_CbusWakeupInterrupt()
2145 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(5), BIT(5)); // wake up pulse int mask in mhal_mhl_CbusWakeupInterrupt()
2148 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(4), BIT(4)); // Clear wake up pulse int flag in mhal_mhl_CbusWakeupInterrupt()
2163 W2BYTEMSK(REG_MHL_CBUS_00, (ucVenderID << 8), BMASK(15:8)); in mhal_mhl_SetVenderID()
2185 W2BYTEMSK(REG_MHL_CBUS_52, BIT(1), BIT(1)); // CPU write enable in mhal_mhl_LoadEDID()
2189 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address in mhal_mhl_LoadEDID()
2190 W2BYTEMSK(REG_MHL_CBUS_53, edid[ustemp], 0x00FF); // data in mhal_mhl_LoadEDID()
2191 W2BYTEMSK(REG_MHL_CBUS_52, BIT(0), BIT(0)); // write trigger in mhal_mhl_LoadEDID()
2192 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_LoadEDID()
2196 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(1)); // CPU write disable in mhal_mhl_LoadEDID()
2221 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address in mhal_mhl_ReadEDID()
2222 W2BYTEMSK(REG_MHL_CBUS_52, BIT(3), BIT(3)); // read trigger in mhal_mhl_ReadEDID()
2223 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_ReadEDID()
2264 W2BYTEMSK(REG_MHL_CBUS_09, devcap[15], BMASK(7:0)); in mhal_mhl_LoadDeviceCapability()
2286 …W2BYTEMSK(tMHL_INITIAL_TABLE[uctemp].addr, tMHL_INITIAL_TABLE[uctemp].databuf, tMHL_INITIAL_TABLE[… in mhal_mhl_initial()
2291 …W2BYTEMSK(REG_PM_SLEEP_72_L, BIT(6), BIT(6)); // [8]: reg_cbus_debug_sel, [7]: reg_vbus_en_sel , [… in mhal_mhl_initial()
2298 W2BYTEMSK(0x2B28, 0, BIT(11)); in mhal_mhl_initial()
2311 …W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4)|BIT(0), BIT(4)|BIT(1)|BIT(0)); // [1]: receive packet valid mask in mhal_mhl_initial()
2325 W2BYTEMSK(0x001102, BIT(7), BIT(7)); in mhal_mhl_initial()
2326 W2BYTEMSK(0x001128, BIT(0), BIT(0)); in mhal_mhl_initial()
2353 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11)); in mhal_mhl_InvertCableDetect()
2373 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11)); in mhal_mhl_InvertCableDetect()
2383 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11)); in mhal_mhl_InvertCableDetect()
2419 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
2420 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
2424 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
2431 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
2435 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
2459 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
2460 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
2464 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
2471 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
2475 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
2489 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
2490 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
2494 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
2501 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
2505 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
2660 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(0), BIT(0)); in mhal_mhl_CbusIsMscMsgReceived()
2682 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(0), BIT(0)); in mhal_mhl_CbusStucktoLowFlag()
2704 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(4), BIT(4)); in mhal_mhl_CbusWakeupIntFlag()
2737 W2BYTEMSK(REG_MHL_CBUS_25, BIT(12), BIT(12)); // trigger to send in mhal_mhl_CBusWrite()
2757 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(12), BIT(12)); in mhal_mhl_Cbus_SetPathEn()
2761 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(13), BIT(13)); in mhal_mhl_Cbus_SetPathEn()
2825 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in mhal_mhl_CbusIntCB()
2848 W2BYTEMSK(REG_HDMI_04_L, BIT(1), BIT(1)); in mhal_mhl_CBusCheckBCHError()
3107 …W2BYTEMSK(tMHL_POWER_ON_TABLE[uctemp].addr, tMHL_POWER_ON_TABLE[uctemp].databuf, tMHL_POWER_ON_TAB… in mhal_mhl_LoadPowerOnTbl()
3124 …W2BYTEMSK(tMHL_POWER_SAVING_TABLE[uctemp].addr, tMHL_POWER_SAVING_TABLE[uctemp].databuf, tMHL_POWE… in mhal_mhl_LoadPowerStandbyTbl()
3142 …W2BYTEMSK(tMHL_POWER_DOWN_TABLE[uctemp].addr, tMHL_POWER_DOWN_TABLE[uctemp].databuf, tMHL_POWER_DO… in mhal_mhl_LoadPowerDownTbl()
3163 W2BYTEMSK(REG_PM_SLEEP_73_L, BIT(0), BIT(0)); // [0]: reg_hplugc_mhl_en in mhal_mhl_SetHPD()
3167 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(3), BMASK(4:3)); // [4]: output val, [3]: oen in mhal_mhl_SetHPD()
3172 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(4:3)); // [4]: output val, [3]: oen in mhal_mhl_SetHPD()
3220 W2BYTEMSK(REG_MHL_CBUS_10, BIT(15), BIT(15)); in mhal_mhl_GetSRAMReceiveData()
3244 W2BYTEMSK(0x001106, BIT(10), BIT(10)); in mhal_mhl_TestSignal()
3248 W2BYTEMSK(0x001106, 0, BIT(10)); in mhal_mhl_TestSignal()