Lines Matching refs:W2BYTEMSK
410 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
411 … W2BYTEMSK(REG_COMBO_PHY0_P0_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_HdmiBypassModeSetting()
412 W2BYTEMSK(REG_COMBO_PHY0_P0_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
413 W2BYTEMSK(REG_HDCP_DUAL_P0_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
414 W2BYTEMSK(REG_COMBO_PHY0_P0_6F_L, 0, BIT(10)); // I-control PD overwrite write in _mhal_mhl_HdmiBypassModeSetting()
415 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
416 W2BYTEMSK(REG_COMBO_PHY0_P0_11_L, 0, BMASK(12:0)); in _mhal_mhl_HdmiBypassModeSetting()
417 W2BYTEMSK(REG_COMBO_PHY0_P0_6E_L, BIT(8), BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
426 … W2BYTEMSK(REG_COMBO_PHY0_P0_6B_L, (pMHLSignalStatus->ucImpedanceValue << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
434 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
435 … W2BYTEMSK(REG_COMBO_PHY0_P1_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_HdmiBypassModeSetting()
436 W2BYTEMSK(REG_COMBO_PHY0_P1_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
437 W2BYTEMSK(REG_HDCP_DUAL_P1_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
438 W2BYTEMSK(REG_COMBO_PHY0_P1_6F_L, 0, BIT(10)); // I-control PD overwrite write in _mhal_mhl_HdmiBypassModeSetting()
439 …W2BYTEMSK(REG_COMBO_PHY0_P1_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
440 W2BYTEMSK(REG_COMBO_PHY0_P1_11_L, 0, BMASK(12:0)); in _mhal_mhl_HdmiBypassModeSetting()
441 W2BYTEMSK(REG_COMBO_PHY0_P1_6E_L, BIT(8), BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
450 … W2BYTEMSK(REG_COMBO_PHY0_P1_6B_L, (pMHLSignalStatus->ucImpedanceValue << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
458 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
459 … W2BYTEMSK(REG_COMBO_PHY0_P2_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_HdmiBypassModeSetting()
460 W2BYTEMSK(REG_COMBO_PHY0_P2_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
461 W2BYTEMSK(REG_HDCP_DUAL_P2_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
462 W2BYTEMSK(REG_COMBO_PHY0_P2_6F_L, 0, BIT(10)); // I-control PD overwrite write in _mhal_mhl_HdmiBypassModeSetting()
463 …W2BYTEMSK(REG_COMBO_PHY0_P2_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
464 W2BYTEMSK(REG_COMBO_PHY0_P2_11_L, 0, BMASK(12:0)); in _mhal_mhl_HdmiBypassModeSetting()
465 W2BYTEMSK(REG_COMBO_PHY0_P2_6E_L, BIT(8), BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
474 … W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, (pMHLSignalStatus->ucImpedanceValue << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
482 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
483 … W2BYTEMSK(REG_COMBO_PHY0_P3_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_HdmiBypassModeSetting()
484 W2BYTEMSK(REG_COMBO_PHY0_P3_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
485 W2BYTEMSK(REG_HDCP_DUAL_P3_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
486 W2BYTEMSK(REG_COMBO_PHY0_P3_6F_L, 0, BIT(10)); // I-control PD overwrite write in _mhal_mhl_HdmiBypassModeSetting()
487 …W2BYTEMSK(REG_COMBO_PHY0_P3_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
488 W2BYTEMSK(REG_COMBO_PHY0_P3_11_L, 0, BMASK(12:0)); in _mhal_mhl_HdmiBypassModeSetting()
489 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BIT(8), BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
498 … W2BYTEMSK(REG_COMBO_PHY0_P3_6B_L, (pMHLSignalStatus->ucImpedanceValue << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
530 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, BIT(6), BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel m… in _mhal_mhl_Mhl24bitsModeSetting()
531 W2BYTEMSK(REG_COMBO_PHY0_P0_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_Mhl24bitsModeSetting()
532 W2BYTEMSK(REG_COMBO_PHY0_P0_5B_L, 0, BIT(13)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
533 W2BYTEMSK(REG_HDCP_DUAL_P0_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_Mhl24bitsModeSetting()
534 W2BYTEMSK(REG_COMBO_PHY0_P0_6F_L, BIT(10), BIT(10)); // I-control PD overwrite write in _mhal_mhl_Mhl24bitsModeSetting()
535 … W2BYTEMSK(REG_COMBO_PHY0_P0_6C_L, (MHL_ICONTROL_PD_20_VALUE << 9), BMASK(13:9)); // I-control PD in _mhal_mhl_Mhl24bitsModeSetting()
536 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time v… in _mhal_mhl_Mhl24bitsModeSetting()
537 W2BYTEMSK(REG_COMBO_PHY0_P0_11_L, BIT(12) |0x30, BMASK(12:0)); in _mhal_mhl_Mhl24bitsModeSetting()
538 W2BYTEMSK(REG_COMBO_PHY1_P0_10_L, 0, BMASK(1:0)); in _mhal_mhl_Mhl24bitsModeSetting()
559 W2BYTEMSK(REG_COMBO_PHY0_P0_6B_L, usImpedanceSetting, BMASK(15:12)); in _mhal_mhl_Mhl24bitsModeSetting()
567 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, BIT(6), BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel m… in _mhal_mhl_Mhl24bitsModeSetting()
568 W2BYTEMSK(REG_COMBO_PHY0_P1_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_Mhl24bitsModeSetting()
569 W2BYTEMSK(REG_COMBO_PHY0_P1_5B_L, 0, BIT(13)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
570 W2BYTEMSK(REG_HDCP_DUAL_P1_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_Mhl24bitsModeSetting()
571 W2BYTEMSK(REG_COMBO_PHY0_P1_6F_L, BIT(10), BIT(10)); // I-control PD overwrite write in _mhal_mhl_Mhl24bitsModeSetting()
572 … W2BYTEMSK(REG_COMBO_PHY0_P1_6C_L, (MHL_ICONTROL_PD_20_VALUE << 9), BMASK(13:9)); // I-control PD in _mhal_mhl_Mhl24bitsModeSetting()
573 …W2BYTEMSK(REG_COMBO_PHY0_P1_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time v… in _mhal_mhl_Mhl24bitsModeSetting()
574 W2BYTEMSK(REG_COMBO_PHY0_P1_11_L, BIT(12) |0x30, BMASK(12:0)); in _mhal_mhl_Mhl24bitsModeSetting()
575 W2BYTEMSK(REG_COMBO_PHY1_P1_10_L, 0, BMASK(1:0)); in _mhal_mhl_Mhl24bitsModeSetting()
596 W2BYTEMSK(REG_COMBO_PHY0_P1_6B_L, usImpedanceSetting, BMASK(15:12)); in _mhal_mhl_Mhl24bitsModeSetting()
604 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_27_L, BIT(6), BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel m… in _mhal_mhl_Mhl24bitsModeSetting()
605 W2BYTEMSK(REG_COMBO_PHY0_P2_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_Mhl24bitsModeSetting()
606 W2BYTEMSK(REG_COMBO_PHY0_P2_5B_L, 0, BIT(13)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
607 W2BYTEMSK(REG_HDCP_DUAL_P2_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_Mhl24bitsModeSetting()
608 W2BYTEMSK(REG_COMBO_PHY0_P2_6F_L, BIT(10), BIT(10)); // I-control PD overwrite write in _mhal_mhl_Mhl24bitsModeSetting()
609 … W2BYTEMSK(REG_COMBO_PHY0_P2_6C_L, (MHL_ICONTROL_PD_20_VALUE << 9), BMASK(13:9)); // I-control PD in _mhal_mhl_Mhl24bitsModeSetting()
610 …W2BYTEMSK(REG_COMBO_PHY0_P2_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time v… in _mhal_mhl_Mhl24bitsModeSetting()
611 W2BYTEMSK(REG_COMBO_PHY0_P2_11_L, BIT(12) |0x30, BMASK(12:0)); in _mhal_mhl_Mhl24bitsModeSetting()
612 W2BYTEMSK(REG_COMBO_PHY1_P2_10_L, 0, BMASK(1:0)); in _mhal_mhl_Mhl24bitsModeSetting()
633 W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, usImpedanceSetting, BMASK(15:12)); in _mhal_mhl_Mhl24bitsModeSetting()
641 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_27_L, BIT(6), BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel m… in _mhal_mhl_Mhl24bitsModeSetting()
642 W2BYTEMSK(REG_COMBO_PHY0_P3_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_Mhl24bitsModeSetting()
643 W2BYTEMSK(REG_COMBO_PHY0_P3_5B_L, 0, BIT(13)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
644 W2BYTEMSK(REG_HDCP_DUAL_P3_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_Mhl24bitsModeSetting()
645 W2BYTEMSK(REG_COMBO_PHY0_P3_6F_L, BIT(10), BIT(10)); // I-control PD overwrite write in _mhal_mhl_Mhl24bitsModeSetting()
646 … W2BYTEMSK(REG_COMBO_PHY0_P3_6C_L, (MHL_ICONTROL_PD_20_VALUE << 9), BMASK(13:9)); // I-control PD in _mhal_mhl_Mhl24bitsModeSetting()
647 …W2BYTEMSK(REG_COMBO_PHY0_P3_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time v… in _mhal_mhl_Mhl24bitsModeSetting()
648 W2BYTEMSK(REG_COMBO_PHY0_P3_11_L, BIT(12) |0x30, BMASK(12:0)); in _mhal_mhl_Mhl24bitsModeSetting()
649 W2BYTEMSK(REG_COMBO_PHY1_P3_10_L, 0, BMASK(1:0)); in _mhal_mhl_Mhl24bitsModeSetting()
670 W2BYTEMSK(REG_COMBO_PHY0_P3_6B_L, usImpedanceSetting, BMASK(15:12)); in _mhal_mhl_Mhl24bitsModeSetting()
700 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, BIT(1), BIT(1)); // [1]: MHL pack-pixel mode in _mhal_mhl_MhlPackedPixelModeSetting()
701 W2BYTEMSK(REG_HDCP_DUAL_P0_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_MhlPackedPixelModeSetting()
708 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, BIT(1), BIT(1)); // [1]: MHL pack-pixel mode in _mhal_mhl_MhlPackedPixelModeSetting()
709 W2BYTEMSK(REG_HDCP_DUAL_P1_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_MhlPackedPixelModeSetting()
716 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_27_L, BIT(1), BIT(1)); // [1]: MHL pack-pixel mode in _mhal_mhl_MhlPackedPixelModeSetting()
717 W2BYTEMSK(REG_HDCP_DUAL_P2_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_MhlPackedPixelModeSetting()
724 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_27_L, BIT(1), BIT(1)); // [1]: MHL pack-pixel mode in _mhal_mhl_MhlPackedPixelModeSetting()
725 W2BYTEMSK(REG_HDCP_DUAL_P3_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_MhlPackedPixelModeSetting()
754 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
755 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
759 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(2), BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
760 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
764 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(3:1), BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
765 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(0), BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
775 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
776 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
780 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(6), BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
781 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
785 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(7:5), BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
786 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(4), BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
796 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(11:9));// data R-term in _mhal_mhl_RxRtermControl()
797 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(8));// clock R-term in _mhal_mhl_RxRtermControl()
801 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(10), BMASK(11:9));// data R-term in _mhal_mhl_RxRtermControl()
802 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(8));// clock R-term in _mhal_mhl_RxRtermControl()
806 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(11:9), BMASK(11:9));// data R-term in _mhal_mhl_RxRtermControl()
807 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(8), BIT(8));// clock R-term in _mhal_mhl_RxRtermControl()
817 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(15:13));// data R-term in _mhal_mhl_RxRtermControl()
818 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(12));// clock R-term in _mhal_mhl_RxRtermControl()
822 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(14), BMASK(15:13));// data R-term in _mhal_mhl_RxRtermControl()
823 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(12));// clock R-term in _mhal_mhl_RxRtermControl()
827 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(15:13), BMASK(15:13));// data R-term in _mhal_mhl_RxRtermControl()
828 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(12), BIT(12));// clock R-term in _mhal_mhl_RxRtermControl()
852 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in _mhal_mhl_CbusForceToStandby()
853 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(15), BIT(15)); // force enter PM mode in _mhal_mhl_CbusForceToStandby()
868 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(14), BIT(14)); in _mhal_mhl_MHLForceToAttach()
888 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, bflag ? 0 : BIT(0), BIT(0)); // [0]: MHL mac enable in _mhal_mhl_AdjustCommonModeResistor()
894 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, bflag ? 0 : BIT(0), BIT(0)); // [0]: MHL mac enable in _mhal_mhl_AdjustCommonModeResistor()
900 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_27_L, bflag ? 0 : BIT(0), BIT(0)); // [0]: MHL mac enable in _mhal_mhl_AdjustCommonModeResistor()
906 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_27_L, bflag ? 0 : BIT(0), BIT(0)); // [0]: MHL mac enable in _mhal_mhl_AdjustCommonModeResistor()
1027 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(8): 0, BIT(8)); in _mhal_mhl_RtermHWControl()
1033 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(9): 0, BIT(9)); in _mhal_mhl_RtermHWControl()
1039 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(10): 0, BIT(10)); in _mhal_mhl_RtermHWControl()
1045 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(11): 0, BIT(11)); in _mhal_mhl_RtermHWControl()
1073 W2BYTEMSK(0x102E02, (MHL_SCALER_MUX_SELECT_MHL << 4), BMASK(7:4)); in _mhal_mhl_ChangeScalerMainMux()
1080 W2BYTEMSK(0x102E02, (MHL_SCALER_MUX_SELECT_DVI << 4), BMASK(7:4)); in _mhal_mhl_ChangeScalerMainMux()
1122 W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, 0x6, BMASK(3:0)); in _mhal_mhl_CbusAndClockSelect()
1123 W2BYTEMSK(REG_COMBO_PHY0_P0_47_L, 0x33, BMASK(9:0)); in _mhal_mhl_CbusAndClockSelect()
1124 W2BYTEMSK(REG_COMBO_PHY1_P0_18_L, 0x361, BMASK(9:0)); in _mhal_mhl_CbusAndClockSelect()
1134 W2BYTEMSK(REG_COMBO_PHY0_P1_45_L, 0x6, BMASK(3:0)); in _mhal_mhl_CbusAndClockSelect()
1135 W2BYTEMSK(REG_COMBO_PHY0_P1_47_L, 0x33, BMASK(9:0)); in _mhal_mhl_CbusAndClockSelect()
1136 W2BYTEMSK(REG_COMBO_PHY1_P1_18_L, 0x361, BMASK(9:0)); in _mhal_mhl_CbusAndClockSelect()
1146 W2BYTEMSK(REG_COMBO_PHY0_P2_45_L, 0x6, BMASK(3:0)); in _mhal_mhl_CbusAndClockSelect()
1147 W2BYTEMSK(REG_COMBO_PHY0_P2_47_L, 0x33, BMASK(9:0)); in _mhal_mhl_CbusAndClockSelect()
1148 W2BYTEMSK(REG_COMBO_PHY1_P2_18_L, 0x361, BMASK(9:0)); in _mhal_mhl_CbusAndClockSelect()
1158 W2BYTEMSK(REG_COMBO_PHY0_P3_45_L, 0x6, BMASK(3:0)); in _mhal_mhl_CbusAndClockSelect()
1159 W2BYTEMSK(REG_COMBO_PHY0_P3_47_L, 0x33, BMASK(9:0)); in _mhal_mhl_CbusAndClockSelect()
1160 W2BYTEMSK(REG_COMBO_PHY1_P3_18_L, 0x361, BMASK(9:0)); in _mhal_mhl_CbusAndClockSelect()
1172 W2BYTEMSK(REG_COMBO_GP_TOP_33_L, ucClockSelect, BMASK(2:0)); // [2:0]: mhl port select in _mhal_mhl_CbusAndClockSelect()
1188 W2BYTEMSK(REG_PM_MHL_CBUS_20, bEnable? BIT(7): 0, BIT(7)); in _mhal_mhl_ForcePullDown100K()
1396 …W2BYTEMSK(REG_MHL_ECBUS_PHY_69, 0x35, BMASK(6:4)| BMASK(2:0)); // [6:4]: rasing pattern type, [2:0… in _mhal_mhl_ECbusInitialSetting()
1398 W2BYTEMSK(REG_MHL_ECBUS_PHY_4C, 0x8880, BMASK(15:4)); in _mhal_mhl_ECbusInitialSetting()
1399 W2BYTEMSK(REG_MHL_ECBUS_PHY_4D, 0x8B14, BMASK(15:1)); in _mhal_mhl_ECbusInitialSetting()
1400 W2BYTEMSK(REG_MHL_ECBUS_PHY_4E, 0x001C, BMASK(15:0)); in _mhal_mhl_ECbusInitialSetting()
1401 W2BYTEMSK(REG_MHL_ECBUS_PHY_51, 0x0100, BMASK(15:0)); in _mhal_mhl_ECbusInitialSetting()
1402 W2BYTEMSK(REG_MHL_ECBUS_PHY_56, 0x0200, BMASK(15:0)); in _mhal_mhl_ECbusInitialSetting()
1403 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BMASK(14:13), BMASK(14:13)); // [14:13] in _mhal_mhl_ECbusInitialSetting()
1404 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusInitialSetting()
1405 W2BYTEMSK(REG_MHL_ECBUS_PHY_55, 0, BMASK(15:4)); //[7:0] in _mhal_mhl_ECbusInitialSetting()
1406 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, 0x00F0, BMASK(15:0)); // [7:4]:reg_ecbss_afe_tx_dri_step in _mhal_mhl_ECbusInitialSetting()
1407 W2BYTEMSK(REG_MHL_ECBUS_PHY_78, BIT(0), BIT(0)); in _mhal_mhl_ECbusInitialSetting()
1409 W2BYTEMSK(REG_MHL_ECBUS_0E, 8, BMASK(4:0)); in _mhal_mhl_ECbusInitialSetting()
1410 W2BYTEMSK(REG_MHL_ECBUS_2D, BIT(3), BIT(3)); in _mhal_mhl_ECbusInitialSetting()
1413 W2BYTEMSK(REG_MHL_ECBUS_PHY_7F, BIT(2), BIT(2)); // [2]:reg_rst_aft_clklck_en in _mhal_mhl_ECbusInitialSetting()
1414 …W2BYTEMSK(REG_MHL_ECBUS_00, BMASK(4:3), BMASK(4:3)); // [4]:reg_rst_aft_fail_en, [3]:reg_rst_aft_c… in _mhal_mhl_ECbusInitialSetting()
1417 W2BYTEMSK(REG_MHL_ECBUS_02, BIT(7), BMASK(13:8)| BIT(7)); // [7] in _mhal_mhl_ECbusInitialSetting()
1418 W2BYTEMSK(REG_MHL_ECBUS_PHY_6D, BIT(5), BMASK(6:5)); in _mhal_mhl_ECbusInitialSetting()
1419 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, 0x700, BMASK(11:8)); // [11:8]: in _mhal_mhl_ECbusInitialSetting()
1420 W2BYTEMSK(REG_MHL_ECBUS_PHY_68, 0x30, BMASK(6:4)); // [6:4]: pre-deglitch in _mhal_mhl_ECbusInitialSetting()
1421 …W2BYTEMSK(REG_MHL_ECBUS_PHY_69, 0x50, BMASK(6:4)| BMASK(2:0)); // [6:4]: rasing pattern type, [2:0… in _mhal_mhl_ECbusInitialSetting()
1422 …W2BYTEMSK(REG_MHL_ECBUS_PHY_65, 0x08, BMASK(5:0)); // [5:0]: reg_dat_lsb_mask; after analog rwa da… in _mhal_mhl_ECbusInitialSetting()
1425 …W2BYTEMSK(REG_MHL_ECBUS_77, (_mhal_mhl_GetEMSCOneByteCRC(5) << 8)| _mhal_mhl_GetEMSCOneByteCRC(4),… in _mhal_mhl_ECbusInitialSetting()
1426 …W2BYTEMSK(REG_MHL_ECBUS_78, (_mhal_mhl_GetEMSCOneByteCRC(7) << 8)| _mhal_mhl_GetEMSCOneByteCRC(6),… in _mhal_mhl_ECbusInitialSetting()
1427 …W2BYTEMSK(REG_MHL_ECBUS_79, BIT(11)| (_mhal_mhl_GetEMSCTwoByteCRC(1, 1) << 3)| (_mhal_mhl_GetEMSCT… in _mhal_mhl_ECbusInitialSetting()
1428 W2BYTEMSK(REG_MHL_ECBUS_PHY_13, BIT(4), BIT(4)); // in _mhal_mhl_ECbusInitialSetting()
1429 W2BYTEMSK(REG_MHL_ECBUS_PHY_51, BIT(11), BIT(11)); // in _mhal_mhl_ECbusInitialSetting()
1432 …W2BYTEMSK(REG_MHL_ECBUS_04, 0xE0E, BMASK(14:8)| BMASK(6:0)); // [14:8]: reg_t_sink_cal, [6:0]: reg… in _mhal_mhl_ECbusInitialSetting()
1433 W2BYTEMSK(REG_MHL_ECBUS_06, 0x1C00, BMASK(14:8)); // [14:8]: reg_t_snk_tdm; in _mhal_mhl_ECbusInitialSetting()
1434 …W2BYTEMSK(REG_MHL_ECBUS_03, BMASK(15:14), BMASK(15:14)); // [15]:reg_wait_tdm_timer_dis [14]:reg_w… in _mhal_mhl_ECbusInitialSetting()
1435 W2BYTEMSK(REG_MHL_ECBUS_07, 0x104, BMASK(14:8)| BMASK(6:0)); // [14:8]: reg_t_snk_tdm; in _mhal_mhl_ECbusInitialSetting()
1436 W2BYTEMSK(REG_MHL_ECBUS_3F, 0, BMASK(1:0)); // in _mhal_mhl_ECbusInitialSetting()
1437 W2BYTEMSK(REG_MHL_ECBUS_48, 0, BMASK(2:0)); // in _mhal_mhl_ECbusInitialSetting()
1440 …W2BYTEMSK(REG_MHL_ECBUS_PHY_70, 0x032B, BMASK(15:0)); // [15:0]:reg_crlock_mid; the CR lock refere… in _mhal_mhl_ECbusInitialSetting()
1441 …W2BYTEMSK(REG_MHL_ECBUS_PHY_71, 0x0C04, BMASK(15:0)); // [15:8]:reg_crlock_thr, the CR lock refere… in _mhal_mhl_ECbusInitialSetting()
1442 …W2BYTEMSK(REG_MHL_ECBUS_PHY_72, 0x0007, BMASK(15:0)); // [12:8]:reg_cr_unlock_num, clock unlock th… in _mhal_mhl_ECbusInitialSetting()
1446 …W2BYTEMSK(REG_MHL_ECBUS_PHY_5C, 0x010A, BMASK(15:0)); // [10:8]:reg_txloc_golden_lowr_tol, [5:0… in _mhal_mhl_ECbusInitialSetting()
1447 …W2BYTEMSK(REG_MHL_ECBUS_PHY_66, 0x2117, BMASK(15:0)); // [14:12]:reg_txloc_golden2_tol, [10:8]:re… in _mhal_mhl_ECbusInitialSetting()
1448 …W2BYTEMSK(REG_MHL_ECBUS_PHY_67, 0x0403, BMASK(15:0)); // [14:12]:reg_val_aft_adj_ok, [10:8]:reg_tx… in _mhal_mhl_ECbusInitialSetting()
1449 W2BYTEMSK(REG_MHL_ECBUS_PHY_69, BIT(10), BMASK(11:10)); // [11:10]:reg_txloc_set_time in _mhal_mhl_ECbusInitialSetting()
1450 …W2BYTEMSK(REG_MHL_ECBUS_PHY_6A, 0xf117, BMASK(15:0)); // [15:12]:reg_txloc_lck_thr, [10:8]:reg_txl… in _mhal_mhl_ECbusInitialSetting()
1454 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(8)| 0x22, BIT(8)| BMASK(7:4)); in _mhal_mhl_ECbusInitialSetting()
1457 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(8)| 0x00, BIT(8)| BMASK(7:4)); in _mhal_mhl_ECbusInitialSetting()
1460 W2BYTEMSK(REG_MHL_ECBUS_PHY_6D, BIT(8), BIT(8)); in _mhal_mhl_ECbusInitialSetting()
1462 W2BYTEMSK(REG_MHL_ECBUS_PHY_6C, 0x0000, BMASK(15:0)); in _mhal_mhl_ECbusInitialSetting()
1481 W2BYTEMSK(REG_MHL_ECBUS_36, 0, BIT(0)); // Ecbus state change int mask in _mhal_mhl_SetECbusStateChangeInterrupt()
1485 W2BYTEMSK(REG_MHL_ECBUS_36, BIT(0), BIT(0)); // Ecbus state change int mask in _mhal_mhl_SetECbusStateChangeInterrupt()
1488 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); // Ecbus state change int clear in _mhal_mhl_SetECbusStateChangeInterrupt()
1503 W2BYTEMSK(REG_MHL_ECBUS_36, bEnableFlag? 0: BIT(12), BIT(12)); // eMSC receive int mask in _mhal_mhl_SetEMSCReceiveInterrupt()
1504 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); // eMSC receive int clear in _mhal_mhl_SetEMSCReceiveInterrupt()
1519 …W2BYTEMSK(REG_PM_MHL_CBUS_0B, bEnableFlag? MHL_CBUS_CONNECT_CHECK_VALUE: 0, BMASK(15:0)); // [15:0… in _mhal_mhl_CbusConnectCheckEnable()
1534 W2BYTEMSK(REG_MHL_ECBUS_PHY_4D, bEnableFlag? 0: BIT(0), BIT(0)); // ECbus PLL pd in _mhal_mhl_ECbusEnableSetting()
1536 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, bEnableFlag? BIT(3): BIT(2), BMASK(3:2)); // in _mhal_mhl_ECbusEnableSetting()
1537 W2BYTEMSK(REG_MHL_ECBUS_PHY_6F, bEnableFlag? BIT(8): 0, BIT(8)); // ECbus clock detect in _mhal_mhl_ECbusEnableSetting()
1538 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, bEnableFlag? 0: BIT(13), BIT(13)); in _mhal_mhl_ECbusEnableSetting()
1539 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, bEnableFlag? 0: BIT(13), BIT(13)); in _mhal_mhl_ECbusEnableSetting()
1543 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(13), BIT(13)); // [13]: ECbus on in _mhal_mhl_ECbusEnableSetting()
1547 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(14), BIT(14)); // [14]: ECbus off in _mhal_mhl_ECbusEnableSetting()
1568 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, 0, BIT(13)); in _mhal_mhl_ECbusBISTSetting()
1569 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, 0, BIT(13)); in _mhal_mhl_ECbusBISTSetting()
1571 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(14), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1572 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(14), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1581 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1582 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1586 W2BYTEMSK(REG_MHL_ECBUS_PHY_56, BIT(8), BIT(8)); in _mhal_mhl_ECbusBISTSetting()
1587 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1588 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, 0, BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1598 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(14), BIT(14)); // [14]: ECbus off in _mhal_mhl_ECbusBISTSetting()
1601 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(13), BIT(13)); in _mhal_mhl_ECbusBISTSetting()
1602 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(13), BIT(13)); in _mhal_mhl_ECbusBISTSetting()
1604 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1605 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1607 W2BYTEMSK(REG_MHL_ECBUS_PHY_56, 0, BIT(8)); in _mhal_mhl_ECbusBISTSetting()
1623 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, bEnableFlag? BIT(3): 0, BIT(3)); // [3]: Enable ECbus dmux in _mhal_mhl_ECbusDmuxEnable()
1638 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(0), BIT(0)); in _mhal_mhl_CbusEngineReset()
1639 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(0)); in _mhal_mhl_CbusEngineReset()
1654 W2BYTEMSK(REG_MHL_ECBUS_00, BMASK(1:0), BMASK(1:0)); // ECbus state reset in _mhal_mhl_ECbusStateReset()
1655 W2BYTEMSK(REG_MHL_ECBUS_00, 0, BMASK(1:0)); // ECbus state reset in _mhal_mhl_ECbusStateReset()
1670 …W2BYTEMSK(REG_MHL_CBUS_17, bECbusEnable? 0x7000: 0x0800, BMASK(15:8)); // [15:8]: reg_ddc_hdcp_sho… in _mhal_mhl_SetShortReadAddress()
1686 W2BYTEMSK(REG_MHL_ECBUS_0F, bEnableFlag? (BIT(8)| 0x4): 0, BIT(8)| BMASK(3:0)); in _mhal_mhl_ECbusStateOverwrite()
1705 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_60_L, bEnableFlag? BMASK(10:8): 0, BMASK(10:8)); // [8]: MHL3 engin… in _mhal_mhl_Version3PhyEnable()
1706 …W2BYTEMSK(REG_COMBO_PHY0_P0_73_L, bEnableFlag? MHL_EQ_30_SETTING_VALUE: MHL_EQ_20_SETTING_VALUE, B… in _mhal_mhl_Version3PhyEnable()
1707 …W2BYTEMSK(REG_COMBO_PHY0_P0_6C_L, ((bEnableFlag? MHL_ICONTROL_PD_30_VALUE: MHL_ICONTROL_PD_20_VALU… in _mhal_mhl_Version3PhyEnable()
1708 W2BYTEMSK(REG_COMBO_PHY0_P0_60_L, bEnableFlag? 0: BIT(5), BIT(5)); in _mhal_mhl_Version3PhyEnable()
1715 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_60_L, bEnableFlag? BMASK(10:8): 0, BMASK(10:8)); // [8]: MHL3 engin… in _mhal_mhl_Version3PhyEnable()
1716 …W2BYTEMSK(REG_COMBO_PHY0_P1_73_L, bEnableFlag? MHL_EQ_30_SETTING_VALUE: MHL_EQ_20_SETTING_VALUE, B… in _mhal_mhl_Version3PhyEnable()
1717 …W2BYTEMSK(REG_COMBO_PHY0_P1_6C_L, ((bEnableFlag? MHL_ICONTROL_PD_30_VALUE: MHL_ICONTROL_PD_20_VALU… in _mhal_mhl_Version3PhyEnable()
1718 W2BYTEMSK(REG_COMBO_PHY0_P1_60_L, bEnableFlag? 0: BIT(5), BIT(5)); in _mhal_mhl_Version3PhyEnable()
1725 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_60_L, bEnableFlag? BMASK(10:8): 0, BMASK(10:8)); // [8]: MHL3 engin… in _mhal_mhl_Version3PhyEnable()
1726 …W2BYTEMSK(REG_COMBO_PHY0_P2_73_L, bEnableFlag? MHL_EQ_30_SETTING_VALUE: MHL_EQ_20_SETTING_VALUE, B… in _mhal_mhl_Version3PhyEnable()
1727 …W2BYTEMSK(REG_COMBO_PHY0_P2_6C_L, ((bEnableFlag? MHL_ICONTROL_PD_30_VALUE: MHL_ICONTROL_PD_20_VALU… in _mhal_mhl_Version3PhyEnable()
1728 W2BYTEMSK(REG_COMBO_PHY0_P2_60_L, bEnableFlag? 0: BIT(5), BIT(5)); in _mhal_mhl_Version3PhyEnable()
1735 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_60_L, bEnableFlag? BMASK(10:8): 0, BMASK(10:8)); // [8]: MHL3 engin… in _mhal_mhl_Version3PhyEnable()
1736 …W2BYTEMSK(REG_COMBO_PHY0_P3_73_L, bEnableFlag? MHL_EQ_30_SETTING_VALUE: MHL_EQ_20_SETTING_VALUE, B… in _mhal_mhl_Version3PhyEnable()
1737 …W2BYTEMSK(REG_COMBO_PHY0_P3_6C_L, ((bEnableFlag? MHL_ICONTROL_PD_30_VALUE: MHL_ICONTROL_PD_20_VALU… in _mhal_mhl_Version3PhyEnable()
1738 W2BYTEMSK(REG_COMBO_PHY0_P3_60_L, bEnableFlag? 0: BIT(5), BIT(5)); in _mhal_mhl_Version3PhyEnable()
1765 W2BYTEMSK(REG_MHL_ECBUS_3D, BIT(1), BIT(1)); in _mhal_mhl_SetECbusBISTTrigger()
1766 W2BYTEMSK(REG_MHL_ECBUS_2A, BIT(12), BMASK(13:12)); in _mhal_mhl_SetECbusBISTTrigger()
1770 W2BYTEMSK(REG_MHL_ECBUS_2A, BIT(13), BMASK(13:12)); in _mhal_mhl_SetECbusBISTTrigger()
1771 W2BYTEMSK(REG_MHL_ECBUS_3D, 0, BIT(1)); in _mhal_mhl_SetECbusBISTTrigger()
1777 W2BYTEMSK(REG_MHL_ECBUS_2E, bEnableFlag? BIT(12): BIT(13), BMASK(13:12)); in _mhal_mhl_SetECbusBISTTrigger()
1821 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(4), BIT(4)); // [4]: clear PLL lock status in _mhal_mhl_ECbusModeUpProc()
1822 W2BYTEMSK(REG_MHL_ECBUS_34, 0, BIT(4)); // [4]: clear PLL lock status in _mhal_mhl_ECbusModeUpProc()
1826 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(13), BIT(13)); in _mhal_mhl_ECbusModeUpProc()
1827 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:12), BMASK(14:12)); // delay in _mhal_mhl_ECbusModeUpProc()
1844 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(13), BIT(13)); in _mhal_mhl_ECbusModeDownProc()
1859 …W2BYTEMSK(REG_HDMI2_DUAL_0_54_L, bLinkRate6GFlag? 0: BIT(1), BMASK(1:0)); // [1:0]: reg_avg_ctrl_c… in _mhal_mhl_MHL3MuxSetting0()
1874 W2BYTEMSK(REG_MHL_ECBUS_23, BIT(15), BIT(15)); in _mhal_mhl_GetSRAMReceiveEMSCData()
1893 W2BYTEMSK(REG_MHL_ECBUS_20, ucSendEMSC, BMASK(7:0)); in _mhal_mhl_InsertSRAMSendEMSCData()
1895 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(15), BIT(15)); in _mhal_mhl_InsertSRAMSendEMSCData()
2084 …W2BYTEMSK(REG_MHL_ECBUS_7A, bEnableFlag? BIT(5)| BIT(4)| BMASK(3:0): 0, BIT(5)| BIT(4)| BMASK(3:0)… in _mhal_mhl_BISTECbusEnable()
2085 W2BYTEMSK(REG_MHL_ECBUS_06, bEnableFlag? 0x1800: 0x1C00, BMASK(14:8)); in _mhal_mhl_BISTECbusEnable()
2086 W2BYTEMSK(REG_MHL_ECBUS_2D, bEnableFlag? BIT(4): BIT(5), BMASK(5:4)); in _mhal_mhl_BISTECbusEnable()
2105 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_76_L, bEnableFlag? BIT(0): BIT(2), BIT(2)| BIT(0)); in _mhal_mhl_BISTAVLinkEnable()
2109 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_76_L, BIT(1), BIT(1)); in _mhal_mhl_BISTAVLinkEnable()
2110 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_76_L, 0, BIT(1)); in _mhal_mhl_BISTAVLinkEnable()
2118 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_76_L, bEnableFlag? BIT(0): BIT(2), BIT(2)| BIT(0)); in _mhal_mhl_BISTAVLinkEnable()
2122 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_76_L, BIT(1), BIT(1)); in _mhal_mhl_BISTAVLinkEnable()
2123 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_76_L, 0, BIT(1)); in _mhal_mhl_BISTAVLinkEnable()
2131 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_76_L, bEnableFlag? BIT(0): BIT(2), BIT(2)| BIT(0)); in _mhal_mhl_BISTAVLinkEnable()
2135 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_76_L, BIT(1), BIT(1)); in _mhal_mhl_BISTAVLinkEnable()
2136 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_76_L, 0, BIT(1)); in _mhal_mhl_BISTAVLinkEnable()
2144 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_76_L, bEnableFlag? BIT(0): BIT(2), BIT(2)| BIT(0)); in _mhal_mhl_BISTAVLinkEnable()
2148 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_76_L, BIT(1), BIT(1)); in _mhal_mhl_BISTAVLinkEnable()
2149 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_76_L, 0, BIT(1)); in _mhal_mhl_BISTAVLinkEnable()
2290 W2BYTEMSK(REG_COMBO_PHY1_P0_45_L, MHL_COARSE_TUNE_30_MIN, BMASK(4:0)); in _mhal_mhl_MHL30AutoEQSetting()
2291 W2BYTEMSK(REG_COMBO_PHY1_P0_49_L, BIT(5), BIT(5)); in _mhal_mhl_MHL30AutoEQSetting()
2292 W2BYTEMSK(REG_COMBO_PHY0_P0_29_L, BIT(8), BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2293 W2BYTEMSK(REG_COMBO_PHY1_P0_11_L, BIT(4), BIT(4)); in _mhal_mhl_MHL30AutoEQSetting()
2294 W2BYTEMSK(REG_COMBO_PHY1_P0_42_L, MHL_COARSE_TUNE_30_DETECT_TIME, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2295 W2BYTEMSK(REG_COMBO_PHY1_P0_4A_L, MHL_COARSE_TUNE_30_AABA_NUMBER, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2296 W2BYTEMSK(REG_COMBO_PHY1_P0_4B_L, MHL_FINE_TUNE_AABA_30_NUMBER, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2297 W2BYTEMSK(REG_COMBO_PHY1_P0_4C_L, MHL_FINE_TUNE_UNDER_30_THRESHOLD, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2298 W2BYTEMSK(REG_COMBO_PHY0_P0_26_L, BIT(11)| BIT(9), BMASK(13:8)); in _mhal_mhl_MHL30AutoEQSetting()
2305 W2BYTEMSK(REG_COMBO_PHY1_P1_45_L, MHL_COARSE_TUNE_30_MIN, BMASK(4:0)); in _mhal_mhl_MHL30AutoEQSetting()
2306 W2BYTEMSK(REG_COMBO_PHY1_P1_49_L, BIT(5), BIT(5)); in _mhal_mhl_MHL30AutoEQSetting()
2307 W2BYTEMSK(REG_COMBO_PHY0_P1_29_L, BIT(8), BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2308 W2BYTEMSK(REG_COMBO_PHY1_P1_11_L, BIT(4), BIT(4)); in _mhal_mhl_MHL30AutoEQSetting()
2309 W2BYTEMSK(REG_COMBO_PHY1_P1_42_L, MHL_COARSE_TUNE_30_DETECT_TIME, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2310 W2BYTEMSK(REG_COMBO_PHY1_P1_4A_L, MHL_COARSE_TUNE_30_AABA_NUMBER, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2311 W2BYTEMSK(REG_COMBO_PHY1_P1_4B_L, MHL_FINE_TUNE_AABA_30_NUMBER, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2312 W2BYTEMSK(REG_COMBO_PHY1_P1_4C_L, MHL_FINE_TUNE_UNDER_30_THRESHOLD, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2313 W2BYTEMSK(REG_COMBO_PHY0_P1_26_L, BIT(11)| BIT(9), BMASK(13:8)); in _mhal_mhl_MHL30AutoEQSetting()
2320 W2BYTEMSK(REG_COMBO_PHY1_P2_45_L, MHL_COARSE_TUNE_30_MIN, BMASK(4:0)); in _mhal_mhl_MHL30AutoEQSetting()
2321 W2BYTEMSK(REG_COMBO_PHY1_P2_49_L, BIT(5), BIT(5)); in _mhal_mhl_MHL30AutoEQSetting()
2322 W2BYTEMSK(REG_COMBO_PHY0_P2_29_L, BIT(8), BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2323 W2BYTEMSK(REG_COMBO_PHY1_P2_11_L, BIT(4), BIT(4)); in _mhal_mhl_MHL30AutoEQSetting()
2324 W2BYTEMSK(REG_COMBO_PHY1_P2_42_L, MHL_COARSE_TUNE_30_DETECT_TIME, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2325 W2BYTEMSK(REG_COMBO_PHY1_P2_4A_L, MHL_COARSE_TUNE_30_AABA_NUMBER, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2326 W2BYTEMSK(REG_COMBO_PHY1_P2_4B_L, MHL_FINE_TUNE_AABA_30_NUMBER, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2327 W2BYTEMSK(REG_COMBO_PHY1_P2_4C_L, MHL_FINE_TUNE_UNDER_30_THRESHOLD, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2328 W2BYTEMSK(REG_COMBO_PHY0_P2_26_L, BIT(11)| BIT(9), BMASK(13:8)); in _mhal_mhl_MHL30AutoEQSetting()
2335 W2BYTEMSK(REG_COMBO_PHY1_P3_45_L, MHL_COARSE_TUNE_30_MIN, BMASK(4:0)); in _mhal_mhl_MHL30AutoEQSetting()
2336 W2BYTEMSK(REG_COMBO_PHY1_P3_49_L, BIT(5), BIT(5)); in _mhal_mhl_MHL30AutoEQSetting()
2337 W2BYTEMSK(REG_COMBO_PHY0_P3_29_L, BIT(8), BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2338 W2BYTEMSK(REG_COMBO_PHY1_P3_11_L, BIT(4), BIT(4)); in _mhal_mhl_MHL30AutoEQSetting()
2339 W2BYTEMSK(REG_COMBO_PHY1_P3_42_L, MHL_COARSE_TUNE_30_DETECT_TIME, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2340 W2BYTEMSK(REG_COMBO_PHY1_P3_4A_L, MHL_COARSE_TUNE_30_AABA_NUMBER, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2341 W2BYTEMSK(REG_COMBO_PHY1_P3_4B_L, MHL_FINE_TUNE_AABA_30_NUMBER, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2342 W2BYTEMSK(REG_COMBO_PHY1_P3_4C_L, MHL_FINE_TUNE_UNDER_30_THRESHOLD, BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2343 W2BYTEMSK(REG_COMBO_PHY0_P3_26_L, BIT(11)| BIT(9), BMASK(13:8)); in _mhal_mhl_MHL30AutoEQSetting()
2372 W2BYTEMSK(REG_COMBO_PHY0_P0_33_L, BIT(2), BIT(2)); in _mhal_mhl_MHL3AutoEQTrigger()
2376 W2BYTEMSK(REG_COMBO_PHY0_P0_33_L, 0, BIT(2)); in _mhal_mhl_MHL3AutoEQTrigger()
2383 W2BYTEMSK(REG_COMBO_PHY0_P1_33_L, BIT(2), BIT(2)); in _mhal_mhl_MHL3AutoEQTrigger()
2387 W2BYTEMSK(REG_COMBO_PHY0_P1_33_L, 0, BIT(2)); in _mhal_mhl_MHL3AutoEQTrigger()
2394 W2BYTEMSK(REG_COMBO_PHY0_P2_33_L, BIT(2), BIT(2)); in _mhal_mhl_MHL3AutoEQTrigger()
2398 W2BYTEMSK(REG_COMBO_PHY0_P2_33_L, 0, BIT(2)); in _mhal_mhl_MHL3AutoEQTrigger()
2405 W2BYTEMSK(REG_COMBO_PHY0_P3_33_L, BIT(2), BIT(2)); in _mhal_mhl_MHL3AutoEQTrigger()
2409 W2BYTEMSK(REG_COMBO_PHY0_P3_33_L, 0, BIT(2)); in _mhal_mhl_MHL3AutoEQTrigger()
2438 W2BYTEMSK(REG_COMBO_PHY0_P0_41_L, 0, BMASK(15:14)); in _mhal_mhl_GetAutoEQDoneFlag()
2450 W2BYTEMSK(REG_COMBO_PHY0_P1_41_L, 0, BMASK(15:14)); in _mhal_mhl_GetAutoEQDoneFlag()
2462 W2BYTEMSK(REG_COMBO_PHY0_P2_41_L, 0, BMASK(15:14)); in _mhal_mhl_GetAutoEQDoneFlag()
2474 W2BYTEMSK(REG_COMBO_PHY0_P3_41_L, 0, BMASK(15:14)); in _mhal_mhl_GetAutoEQDoneFlag()
2512 W2BYTEMSK(REG_COMBO_PHY0_P0_6E_L, 0, BMASK(7:4)); in _mhal_mhl_MHL30AutoEQEnable()
2513 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, BIT(2), BIT(2)); in _mhal_mhl_MHL30AutoEQEnable()
2519 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, 0, BIT(2)); in _mhal_mhl_MHL30AutoEQEnable()
2520 W2BYTEMSK(REG_COMBO_PHY0_P0_6E_L, BMASK(7:4), BMASK(7:4)); in _mhal_mhl_MHL30AutoEQEnable()
2521 … W2BYTEMSK(REG_COMBO_PHY0_P0_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_MHL30AutoEQEnable()
2524 W2BYTEMSK(REG_COMBO_PHY0_P0_15_L, bAutoEQEnable? BIT(15): 0, BIT(15)); in _mhal_mhl_MHL30AutoEQEnable()
2525 W2BYTEMSK(REG_COMBO_PHY1_P0_44_L, bAutoEQEnable? 0: BIT(0), BIT(0)); in _mhal_mhl_MHL30AutoEQEnable()
2526 W2BYTEMSK(REG_COMBO_PHY1_P0_49_L, bAutoEQEnable? 0: BIT(5), BIT(5)); in _mhal_mhl_MHL30AutoEQEnable()
2527 W2BYTEMSK(REG_COMBO_PHY1_P0_11_L, bAutoEQEnable? 0: BIT(4), BIT(4)); in _mhal_mhl_MHL30AutoEQEnable()
2536 W2BYTEMSK(REG_COMBO_PHY0_P1_6E_L, 0, BMASK(7:4)); in _mhal_mhl_MHL30AutoEQEnable()
2537 W2BYTEMSK(REG_COMBO_PHY0_P1_25_L, BIT(2), BIT(2)); in _mhal_mhl_MHL30AutoEQEnable()
2543 W2BYTEMSK(REG_COMBO_PHY0_P1_25_L, 0, BIT(2)); in _mhal_mhl_MHL30AutoEQEnable()
2544 W2BYTEMSK(REG_COMBO_PHY0_P1_6E_L, BMASK(7:4), BMASK(7:4)); in _mhal_mhl_MHL30AutoEQEnable()
2545 … W2BYTEMSK(REG_COMBO_PHY0_P1_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_MHL30AutoEQEnable()
2548 W2BYTEMSK(REG_COMBO_PHY0_P1_15_L, bAutoEQEnable? BIT(15): 0, BIT(15)); in _mhal_mhl_MHL30AutoEQEnable()
2549 W2BYTEMSK(REG_COMBO_PHY1_P1_44_L, bAutoEQEnable? 0: BIT(0), BIT(0)); in _mhal_mhl_MHL30AutoEQEnable()
2550 W2BYTEMSK(REG_COMBO_PHY1_P1_49_L, bAutoEQEnable? 0: BIT(5), BIT(5)); in _mhal_mhl_MHL30AutoEQEnable()
2551 W2BYTEMSK(REG_COMBO_PHY1_P1_11_L, bAutoEQEnable? 0: BIT(4), BIT(4)); in _mhal_mhl_MHL30AutoEQEnable()
2560 W2BYTEMSK(REG_COMBO_PHY0_P2_6E_L, 0, BMASK(7:4)); in _mhal_mhl_MHL30AutoEQEnable()
2561 W2BYTEMSK(REG_COMBO_PHY0_P2_25_L, BIT(2), BIT(2)); in _mhal_mhl_MHL30AutoEQEnable()
2567 W2BYTEMSK(REG_COMBO_PHY0_P2_25_L, 0, BIT(2)); in _mhal_mhl_MHL30AutoEQEnable()
2568 W2BYTEMSK(REG_COMBO_PHY0_P2_6E_L, BMASK(7:4), BMASK(7:4)); in _mhal_mhl_MHL30AutoEQEnable()
2569 … W2BYTEMSK(REG_COMBO_PHY0_P2_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_MHL30AutoEQEnable()
2572 W2BYTEMSK(REG_COMBO_PHY0_P2_15_L, bAutoEQEnable? BIT(15): 0, BIT(15)); in _mhal_mhl_MHL30AutoEQEnable()
2573 W2BYTEMSK(REG_COMBO_PHY1_P2_44_L, bAutoEQEnable? 0: BIT(0), BIT(0)); in _mhal_mhl_MHL30AutoEQEnable()
2574 W2BYTEMSK(REG_COMBO_PHY1_P2_49_L, bAutoEQEnable? 0: BIT(5), BIT(5)); in _mhal_mhl_MHL30AutoEQEnable()
2575 W2BYTEMSK(REG_COMBO_PHY1_P2_11_L, bAutoEQEnable? 0: BIT(4), BIT(4)); in _mhal_mhl_MHL30AutoEQEnable()
2584 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, 0, BMASK(7:4)); in _mhal_mhl_MHL30AutoEQEnable()
2585 W2BYTEMSK(REG_COMBO_PHY0_P3_25_L, BIT(2), BIT(2)); in _mhal_mhl_MHL30AutoEQEnable()
2591 W2BYTEMSK(REG_COMBO_PHY0_P3_25_L, 0, BIT(2)); in _mhal_mhl_MHL30AutoEQEnable()
2592 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BMASK(7:4), BMASK(7:4)); in _mhal_mhl_MHL30AutoEQEnable()
2593 … W2BYTEMSK(REG_COMBO_PHY0_P3_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_MHL30AutoEQEnable()
2596 W2BYTEMSK(REG_COMBO_PHY0_P3_15_L, bAutoEQEnable? BIT(15): 0, BIT(15)); in _mhal_mhl_MHL30AutoEQEnable()
2597 W2BYTEMSK(REG_COMBO_PHY1_P3_44_L, bAutoEQEnable? 0: BIT(0), BIT(0)); in _mhal_mhl_MHL30AutoEQEnable()
2598 W2BYTEMSK(REG_COMBO_PHY1_P3_49_L, bAutoEQEnable? 0: BIT(5), BIT(5)); in _mhal_mhl_MHL30AutoEQEnable()
2599 W2BYTEMSK(REG_COMBO_PHY1_P3_11_L, bAutoEQEnable? 0: BIT(4), BIT(4)); in _mhal_mhl_MHL30AutoEQEnable()
2755 …W2BYTEMSK(REG_PM_SLEEP_72_L, BMASK(7:6), BMASK(8:6)); // [8]: reg_cbus_debug_sel, [7]: reg_vbus_en… in mhal_mhl_MHLSupportPath()
2927 W2BYTEMSK(REG_COMBO_PHY0_P0_6E_L, 0, BIT(8)); in mhal_mhl_CDRModeMonitor()
2948 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_72_L, BIT(13), BIT(13)); in mhal_mhl_CDRModeMonitor()
2950 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_72_L, 0, BIT(13)); in mhal_mhl_CDRModeMonitor()
2987 W2BYTEMSK(REG_COMBO_PHY0_P0_6E_L, BIT(8), BIT(8)); in mhal_mhl_CDRModeMonitor()
3010 W2BYTEMSK(REG_COMBO_PHY0_P1_6E_L, 0, BIT(8)); in mhal_mhl_CDRModeMonitor()
3031 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_72_L, BIT(13), BIT(13)); in mhal_mhl_CDRModeMonitor()
3033 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_72_L, 0, BIT(13)); in mhal_mhl_CDRModeMonitor()
3070 W2BYTEMSK(REG_COMBO_PHY0_P1_6E_L, BIT(8), BIT(8)); in mhal_mhl_CDRModeMonitor()
3093 W2BYTEMSK(REG_COMBO_PHY0_P2_6E_L, 0, BIT(8)); in mhal_mhl_CDRModeMonitor()
3114 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_72_L, BIT(13), BIT(13)); in mhal_mhl_CDRModeMonitor()
3116 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_72_L, 0, BIT(13)); in mhal_mhl_CDRModeMonitor()
3153 W2BYTEMSK(REG_COMBO_PHY0_P2_6E_L, BIT(8), BIT(8)); in mhal_mhl_CDRModeMonitor()
3176 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, 0, BIT(8)); in mhal_mhl_CDRModeMonitor()
3197 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_72_L, BIT(13), BIT(13)); in mhal_mhl_CDRModeMonitor()
3199 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_72_L, 0, BIT(13)); in mhal_mhl_CDRModeMonitor()
3236 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BIT(8), BIT(8)); in mhal_mhl_CDRModeMonitor()
3274 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
3278 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
3288 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
3292 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
3302 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
3306 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
3316 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
3320 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
3350 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0)); in mhal_mhl_VbusCharge()
3354 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
3358 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0)); in mhal_mhl_VbusCharge()
3368 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0)); in mhal_mhl_VbusCharge()
3372 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
3376 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0)); in mhal_mhl_VbusCharge()
3386 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0)); in mhal_mhl_VbusCharge()
3390 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
3394 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0)); in mhal_mhl_VbusCharge()
3404 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0)); in mhal_mhl_VbusCharge()
3408 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
3412 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0)); in mhal_mhl_VbusCharge()
3438 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(5), BIT(5)); in mhal_mhl_CbusFloating()
3442 W2BYTEMSK(REG_PM_MHL_CBUS_17, 0, BIT(5)); in mhal_mhl_CbusFloating()
3460 W2BYTEMSK(REG_PM_MHL_CBUS_18, 0, BIT(1)); // cbus stuck to low int mask in mhal_mhl_CbusStucktoLow()
3464 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(1), BIT(1)); // cbus stuck to low int mask in mhal_mhl_CbusStucktoLow()
3467 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(0), BIT(0)); // Clear cbus stuck to low int flag in mhal_mhl_CbusStucktoLow()
3484 W2BYTEMSK(REG_PM_MHL_CBUS_18, 0, BIT(5)); // wake up pulse int mask in mhal_mhl_CbusWakeupInterrupt()
3488 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(5), BIT(5)); // wake up pulse int mask in mhal_mhl_CbusWakeupInterrupt()
3491 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(4), BIT(4)); // Clear wake up pulse int flag in mhal_mhl_CbusWakeupInterrupt()
3506 W2BYTEMSK(REG_MHL_CBUS_00, (ucVenderID << 8), BMASK(15:8)); in mhal_mhl_SetVenderID()
3528 W2BYTEMSK(REG_MHL_CBUS_52, BIT(1), BIT(1)); // CPU write enable in mhal_mhl_LoadEDID()
3532 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address in mhal_mhl_LoadEDID()
3533 W2BYTEMSK(REG_MHL_CBUS_53, edid[ustemp], 0x00FF); // data in mhal_mhl_LoadEDID()
3534 W2BYTEMSK(REG_MHL_CBUS_52, BIT(0), BIT(0)); // write trigger in mhal_mhl_LoadEDID()
3535 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_LoadEDID()
3539 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(1)); // CPU write disable in mhal_mhl_LoadEDID()
3564 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address in mhal_mhl_ReadEDID()
3565 W2BYTEMSK(REG_MHL_CBUS_52, BIT(3), BIT(3)); // read trigger in mhal_mhl_ReadEDID()
3566 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_ReadEDID()
3607 W2BYTEMSK(REG_MHL_CBUS_09, devcap[15], BMASK(7:0)); in mhal_mhl_LoadDeviceCapability()
3634 …W2BYTEMSK(tMHL_INITIAL_TABLE[uctemp].addr, tMHL_INITIAL_TABLE[uctemp].databuf, tMHL_INITIAL_TABLE[… in mhal_mhl_initial()
3644 W2BYTEMSK(0x2B28, 0, BIT(11)); in mhal_mhl_initial()
3657 …W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4)|BIT(0), BIT(4)|BIT(1)|BIT(0)); // [1]: receive packet valid mask in mhal_mhl_initial()
3692 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11)); in mhal_mhl_InvertCableDetect()
3698 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11)); in mhal_mhl_InvertCableDetect()
3704 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11)); in mhal_mhl_InvertCableDetect()
3710 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11)); in mhal_mhl_InvertCableDetect()
3742 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3743 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3747 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3754 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3758 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3769 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3770 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3774 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3781 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3785 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3796 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3797 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3801 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3808 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3812 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3823 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3824 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3828 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3835 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3839 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3983 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(0), BIT(0)); in mhal_mhl_CbusIsMscMsgReceived()
4005 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(0), BIT(0)); in mhal_mhl_CbusStucktoLowFlag()
4027 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(4), BIT(4)); in mhal_mhl_CbusWakeupIntFlag()
4049 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); in mhal_mhl_GetECbusStateChangeFlag()
4076 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); in mhal_mhl_GetEMSCReceiveFlag()
4098 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(10), BIT(10)); // eMSC send pass clear in mhal_mhl_GetEMSCSendStatus()
4104 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(9), BIT(9)); // eMSC send fail clear in mhal_mhl_GetEMSCSendStatus()
4137 W2BYTEMSK(REG_MHL_CBUS_25, BIT(12), BIT(12)); // trigger to send in mhal_mhl_CBusWrite()
4175 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(12), BIT(12)); in mhal_mhl_Cbus_SetPathEn()
4179 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(13), BIT(13)); in mhal_mhl_Cbus_SetPathEn()
4243 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in mhal_mhl_CbusIntCB()
4486 …W2BYTEMSK(tMHL_POWER_ON_TABLE[uctemp].addr, tMHL_POWER_ON_TABLE[uctemp].databuf, tMHL_POWER_ON_TAB… in mhal_mhl_LoadPowerOnTbl()
4503 …W2BYTEMSK(tMHL_POWER_SAVING_TABLE[uctemp].addr, tMHL_POWER_SAVING_TABLE[uctemp].databuf, tMHL_POWE… in mhal_mhl_LoadPowerStandbyTbl()
4521 …W2BYTEMSK(tMHL_POWER_DOWN_TABLE[uctemp].addr, tMHL_POWER_DOWN_TABLE[uctemp].databuf, tMHL_POWER_DO… in mhal_mhl_LoadPowerDownTbl()
4544 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(3), BMASK(4:3)); // [4]: output val, [3]: oen in mhal_mhl_SetHPD()
4548 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(4:3)); // [4]: output val, [3]: oen in mhal_mhl_SetHPD()
4595 W2BYTEMSK(REG_MHL_CBUS_10, BIT(15), BIT(15)); in mhal_mhl_GetSRAMReceiveData()
4619 W2BYTEMSK(0x001106, BIT(10), BIT(10)); in mhal_mhl_TestSignal()
4623 W2BYTEMSK(0x001106, 0, BIT(10)); in mhal_mhl_TestSignal()
4658 …W2BYTEMSK(REG_COMBO_PHY1_P0_0D_L, (ucLinkRate << 12), BMASK(13:12)); // [13:12]: Select MHL3 data … in mhal_mhl_SetMainLinkRate()
4674 …W2BYTEMSK(REG_COMBO_PHY1_P1_0D_L, (ucLinkRate << 12), BMASK(13:12)); // [13:12]: Select MHL3 data … in mhal_mhl_SetMainLinkRate()
4690 …W2BYTEMSK(REG_COMBO_PHY1_P2_0D_L, (ucLinkRate << 12), BMASK(13:12)); // [13:12]: Select MHL3 data … in mhal_mhl_SetMainLinkRate()
4706 …W2BYTEMSK(REG_COMBO_PHY1_P3_0D_L, (ucLinkRate << 12), BMASK(13:12)); // [13:12]: Select MHL3 data … in mhal_mhl_SetMainLinkRate()
4743 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, 0, BIT(13)); in mhal_mhl_GetECbusStatusFlag()
4887 …W2BYTEMSK(REG_MHL_ECBUS_2B, usBISTeCbusSettingValue, BMASK(13:12)| BMASK(7:0)); // ecbus bist send… in mhal_mhl_SetBISTParameterInfo()
4888 …W2BYTEMSK(REG_MHL_ECBUS_2F, usBISTeCbusSettingValue, BMASK(13:12)| BMASK(7:0)); // ecbus bist rece… in mhal_mhl_SetBISTParameterInfo()
4904 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_71_L, 0, BIT(0)); in mhal_mhl_SetBISTParameterInfo()
4908 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_71_L, BIT(0), BIT(0)); in mhal_mhl_SetBISTParameterInfo()
4921 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_71_L, 0, BIT(0)); in mhal_mhl_SetBISTParameterInfo()
4925 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_71_L, BIT(0), BIT(0)); in mhal_mhl_SetBISTParameterInfo()
4938 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_71_L, 0, BIT(0)); in mhal_mhl_SetBISTParameterInfo()
4942 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_71_L, BIT(0), BIT(0)); in mhal_mhl_SetBISTParameterInfo()
4955 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_73_L, 0, BIT(0)); in mhal_mhl_SetBISTParameterInfo()
4959 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_73_L, BIT(0), BIT(0)); in mhal_mhl_SetBISTParameterInfo()
5041 W2BYTEMSK(REG_MHL_ECBUS_1C, usEMSCFreeBuffer, BMASK(9:0)); in mhal_mhl_GetEMSCReceiveData()
5042 W2BYTEMSK(REG_MHL_ECBUS_1C, BIT(15), BIT(15)); in mhal_mhl_GetEMSCReceiveData()
5062 W2BYTEMSK(REG_MHL_ECBUS_1B, (ucLength -1), BMASK(9:0)); // Request command byte count in mhal_mhl_InsertEMSCSendData()
5063 …W2BYTEMSK(REG_MHL_ECBUS_79, _mhal_mhl_GetEMSCTwoByteCRC(0, (ucLength -1)) , BMASK(2:0)); // byte c… in mhal_mhl_InsertEMSCSendData()
5065 W2BYTEMSK(REG_MHL_ECBUS_21, 0, BMASK(9:0)); // SRAM address set 0 in mhal_mhl_InsertEMSCSendData()
5066 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(13), BIT(13)); // Trigger address in mhal_mhl_InsertEMSCSendData()
5077 W2BYTEMSK(REG_MHL_ECBUS_19, BIT(15), BIT(15)); // eMSC payload CRC ove in mhal_mhl_InsertEMSCSendData()
5082 W2BYTEMSK(REG_MHL_ECBUS_1B, BIT(15), BIT(15)); // REG_MHL_ECBUS2_1B[15] in mhal_mhl_InsertEMSCSendData()