Lines Matching refs:W2BYTEMSK
409 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
410 … W2BYTEMSK(REG_COMBO_PHY0_P0_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_HdmiBypassModeSetting()
411 W2BYTEMSK(REG_COMBO_PHY0_P0_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
412 W2BYTEMSK(REG_HDCP_DUAL_P0_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
413 W2BYTEMSK(REG_COMBO_PHY0_P0_6F_L, 0, BIT(10)); // I-control PD overwrite write in _mhal_mhl_HdmiBypassModeSetting()
414 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
418 W2BYTEMSK(REG_COMBO_PHY0_P0_59_L, 0, BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
419 W2BYTEMSK(REG_COMBO_PHY0_P0_6B_L, (MHL_IMPEDANCE_VALUE << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
430 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
431 … W2BYTEMSK(REG_COMBO_PHY0_P1_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_HdmiBypassModeSetting()
432 W2BYTEMSK(REG_COMBO_PHY0_P1_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
433 W2BYTEMSK(REG_HDCP_DUAL_P1_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
434 W2BYTEMSK(REG_COMBO_PHY0_P1_6F_L, 0, BIT(10)); // I-control PD overwrite write in _mhal_mhl_HdmiBypassModeSetting()
435 …W2BYTEMSK(REG_COMBO_PHY0_P1_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
439 W2BYTEMSK(REG_COMBO_PHY0_P1_59_L, 0, BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
440 W2BYTEMSK(REG_COMBO_PHY0_P1_6B_L, (MHL_IMPEDANCE_VALUE << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
451 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
452 … W2BYTEMSK(REG_COMBO_PHY0_P2_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_HdmiBypassModeSetting()
453 W2BYTEMSK(REG_COMBO_PHY0_P2_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
454 W2BYTEMSK(REG_HDCP_DUAL_P2_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
455 W2BYTEMSK(REG_COMBO_PHY0_P2_6F_L, 0, BIT(10)); // I-control PD overwrite write in _mhal_mhl_HdmiBypassModeSetting()
456 …W2BYTEMSK(REG_COMBO_PHY0_P2_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
460 W2BYTEMSK(REG_COMBO_PHY0_P2_59_L, 0, BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
461 W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, (MHL_IMPEDANCE_VALUE << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
472 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
473 … W2BYTEMSK(REG_COMBO_PHY0_P3_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_HdmiBypassModeSetting()
474 W2BYTEMSK(REG_COMBO_PHY0_P3_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
475 W2BYTEMSK(REG_HDCP_DUAL_P3_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
476 W2BYTEMSK(REG_COMBO_PHY0_P3_6F_L, 0, BIT(10)); // I-control PD overwrite write in _mhal_mhl_HdmiBypassModeSetting()
477 …W2BYTEMSK(REG_COMBO_PHY0_P3_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock t… in _mhal_mhl_HdmiBypassModeSetting()
481 W2BYTEMSK(REG_COMBO_PHY0_P3_59_L, 0, BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
482 W2BYTEMSK(REG_COMBO_PHY0_P3_6B_L, (MHL_IMPEDANCE_VALUE << 12), BMASK(15:12)); in _mhal_mhl_HdmiBypassModeSetting()
515 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, BIT(6), BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel m… in _mhal_mhl_Mhl24bitsModeSetting()
516 … W2BYTEMSK(REG_COMBO_PHY0_P0_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_Mhl24bitsModeSetting()
517 W2BYTEMSK(REG_COMBO_PHY0_P0_5B_L, 0, BIT(13)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
518 W2BYTEMSK(REG_HDCP_DUAL_P0_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_Mhl24bitsModeSetting()
519 W2BYTEMSK(REG_COMBO_PHY0_P0_6F_L, BIT(10), BIT(10)); // I-control PD overwrite write in _mhal_mhl_Mhl24bitsModeSetting()
520 … W2BYTEMSK(REG_COMBO_PHY0_P0_6C_L, (MHL_ICONTROL_PD_VALUE << 9), BMASK(13:9)); // I-control PD in _mhal_mhl_Mhl24bitsModeSetting()
521 …W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time v… in _mhal_mhl_Mhl24bitsModeSetting()
525 W2BYTEMSK(REG_COMBO_PHY0_P0_59_L, BIT(8), BIT(8)); in _mhal_mhl_Mhl24bitsModeSetting()
526 W2BYTEMSK(REG_COMBO_PHY0_P0_6B_L, (ucImpedanceValue << 12), BMASK(15:12)); in _mhal_mhl_Mhl24bitsModeSetting()
537 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, BIT(6), BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel m… in _mhal_mhl_Mhl24bitsModeSetting()
538 … W2BYTEMSK(REG_COMBO_PHY0_P1_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_Mhl24bitsModeSetting()
539 W2BYTEMSK(REG_COMBO_PHY0_P1_5B_L, 0, BIT(13)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
540 W2BYTEMSK(REG_HDCP_DUAL_P1_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_Mhl24bitsModeSetting()
541 W2BYTEMSK(REG_COMBO_PHY0_P1_6F_L, BIT(10), BIT(10)); // I-control PD overwrite write in _mhal_mhl_Mhl24bitsModeSetting()
542 … W2BYTEMSK(REG_COMBO_PHY0_P1_6C_L, (MHL_ICONTROL_PD_VALUE << 9), BMASK(13:9)); // I-control PD in _mhal_mhl_Mhl24bitsModeSetting()
543 …W2BYTEMSK(REG_COMBO_PHY0_P1_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time v… in _mhal_mhl_Mhl24bitsModeSetting()
547 W2BYTEMSK(REG_COMBO_PHY0_P1_59_L, BIT(8), BIT(8)); in _mhal_mhl_Mhl24bitsModeSetting()
548 W2BYTEMSK(REG_COMBO_PHY0_P1_6B_L, (ucImpedanceValue << 12), BMASK(15:12)); in _mhal_mhl_Mhl24bitsModeSetting()
559 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_27_L, BIT(6), BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel m… in _mhal_mhl_Mhl24bitsModeSetting()
560 … W2BYTEMSK(REG_COMBO_PHY0_P2_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_Mhl24bitsModeSetting()
561 W2BYTEMSK(REG_COMBO_PHY0_P2_5B_L, 0, BIT(13)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
562 W2BYTEMSK(REG_HDCP_DUAL_P2_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_Mhl24bitsModeSetting()
563 W2BYTEMSK(REG_COMBO_PHY0_P2_6F_L, BIT(10), BIT(10)); // I-control PD overwrite write in _mhal_mhl_Mhl24bitsModeSetting()
564 … W2BYTEMSK(REG_COMBO_PHY0_P2_6C_L, (MHL_ICONTROL_PD_VALUE << 9), BMASK(13:9)); // I-control PD in _mhal_mhl_Mhl24bitsModeSetting()
565 …W2BYTEMSK(REG_COMBO_PHY0_P2_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time v… in _mhal_mhl_Mhl24bitsModeSetting()
569 W2BYTEMSK(REG_COMBO_PHY0_P2_59_L, BIT(8), BIT(8)); in _mhal_mhl_Mhl24bitsModeSetting()
570 W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, (ucImpedanceValue << 12), BMASK(15:12)); in _mhal_mhl_Mhl24bitsModeSetting()
581 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_27_L, BIT(6), BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel m… in _mhal_mhl_Mhl24bitsModeSetting()
582 … W2BYTEMSK(REG_COMBO_PHY0_P3_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ in _mhal_mhl_Mhl24bitsModeSetting()
583 W2BYTEMSK(REG_COMBO_PHY0_P3_5B_L, 0, BIT(13)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
584 W2BYTEMSK(REG_HDCP_DUAL_P3_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_Mhl24bitsModeSetting()
585 W2BYTEMSK(REG_COMBO_PHY0_P3_6F_L, BIT(10), BIT(10)); // I-control PD overwrite write in _mhal_mhl_Mhl24bitsModeSetting()
586 … W2BYTEMSK(REG_COMBO_PHY0_P3_6C_L, (MHL_ICONTROL_PD_VALUE << 9), BMASK(13:9)); // I-control PD in _mhal_mhl_Mhl24bitsModeSetting()
587 …W2BYTEMSK(REG_COMBO_PHY0_P3_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time v… in _mhal_mhl_Mhl24bitsModeSetting()
591 W2BYTEMSK(REG_COMBO_PHY0_P3_59_L, BIT(8), BIT(8)); in _mhal_mhl_Mhl24bitsModeSetting()
592 W2BYTEMSK(REG_COMBO_PHY0_P3_6B_L, (ucImpedanceValue << 12), BMASK(15:12)); in _mhal_mhl_Mhl24bitsModeSetting()
625 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, BIT(1), BIT(1)); // [1]: MHL pack-pixel mode in _mhal_mhl_MhlPackedPixelModeSetting()
626 W2BYTEMSK(REG_HDCP_DUAL_P0_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_MhlPackedPixelModeSetting()
636 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, BIT(1), BIT(1)); // [1]: MHL pack-pixel mode in _mhal_mhl_MhlPackedPixelModeSetting()
637 W2BYTEMSK(REG_HDCP_DUAL_P1_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_MhlPackedPixelModeSetting()
647 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_27_L, BIT(1), BIT(1)); // [1]: MHL pack-pixel mode in _mhal_mhl_MhlPackedPixelModeSetting()
648 W2BYTEMSK(REG_HDCP_DUAL_P2_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_MhlPackedPixelModeSetting()
658 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_27_L, BIT(1), BIT(1)); // [1]: MHL pack-pixel mode in _mhal_mhl_MhlPackedPixelModeSetting()
659 W2BYTEMSK(REG_HDCP_DUAL_P3_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_MhlPackedPixelModeSetting()
691 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
692 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
696 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(2), BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
697 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
701 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(3:1), BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
702 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(0), BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
715 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
716 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
720 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(6), BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
721 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
725 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(7:5), BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
726 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(4), BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
739 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(11:9));// data R-term in _mhal_mhl_RxRtermControl()
740 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(8));// clock R-term in _mhal_mhl_RxRtermControl()
744 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(10), BMASK(11:9));// data R-term in _mhal_mhl_RxRtermControl()
745 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(8));// clock R-term in _mhal_mhl_RxRtermControl()
749 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(11:9), BMASK(11:9));// data R-term in _mhal_mhl_RxRtermControl()
750 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(8), BIT(8));// clock R-term in _mhal_mhl_RxRtermControl()
763 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(15:13));// data R-term in _mhal_mhl_RxRtermControl()
764 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(12));// clock R-term in _mhal_mhl_RxRtermControl()
768 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(14), BMASK(15:13));// data R-term in _mhal_mhl_RxRtermControl()
769 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(12));// clock R-term in _mhal_mhl_RxRtermControl()
773 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(15:13), BMASK(15:13));// data R-term in _mhal_mhl_RxRtermControl()
774 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(12), BIT(12));// clock R-term in _mhal_mhl_RxRtermControl()
799 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in _mhal_mhl_CbusForceToStandby()
800 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(15), BIT(15)); // force enter PM mode in _mhal_mhl_CbusForceToStandby()
815 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(14), BIT(14)); in _mhal_mhl_MHLForceToAttach()
837 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, bflag ? 0 : BIT(0), BIT(0)); // [0]: MHL mac enable in _mhal_mhl_AdjustCommonModeResistor()
847 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, bflag ? 0 : BIT(0), BIT(0)); // [0]: MHL mac enable in _mhal_mhl_AdjustCommonModeResistor()
857 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_27_L, bflag ? 0 : BIT(0), BIT(0)); // [0]: MHL mac enable in _mhal_mhl_AdjustCommonModeResistor()
867 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_27_L, bflag ? 0 : BIT(0), BIT(0)); // [0]: MHL mac enable in _mhal_mhl_AdjustCommonModeResistor()
1092 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(8): 0, BIT(8)); in _mhal_mhl_RtermHWControl()
1102 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(9): 0, BIT(9)); in _mhal_mhl_RtermHWControl()
1112 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(10): 0, BIT(10)); in _mhal_mhl_RtermHWControl()
1122 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(11): 0, BIT(11)); in _mhal_mhl_RtermHWControl()
1152 W2BYTEMSK(0x102E02, (MHL_SCALER_MUX_SELECT_MHL << 4), BMASK(7:4)); in _mhal_mhl_ChangeScalerMainMux()
1159 W2BYTEMSK(0x102E02, (MHL_SCALER_MUX_SELECT_DVI << 4), BMASK(7:4)); in _mhal_mhl_ChangeScalerMainMux()
1203 W2BYTEMSK(REG_PM_SLEEP_73_L, BIT(0), BIT(6)| BIT(8)| BIT(0)); // [0]: reg_hplugc_mhl_en in _mhal_mhl_CbusAndClockSelect()
1211 W2BYTEMSK(REG_COMBO_GP_TOP_33_L, ucClockSelect, BMASK(2:0)); // [2:0]: mhl port select in _mhal_mhl_CbusAndClockSelect()
1226 W2BYTEMSK(REG_PM_MHL_CBUS_20, bEnable? BIT(7): 0, BIT(7)); in _mhal_mhl_ForcePullDown100K()
1434 …W2BYTEMSK(REG_MHL_ECBUS_PHY_69, 0x35, BMASK(6:4)| BMASK(2:0)); // [6:4]: rasing pattern type, [2:0… in _mhal_mhl_ECbusInitialSetting()
1436 W2BYTEMSK(REG_MHL_ECBUS_PHY_4C, 0x8880, BMASK(15:4)); in _mhal_mhl_ECbusInitialSetting()
1437 W2BYTEMSK(REG_MHL_ECBUS_PHY_4D, 0x8B14, BMASK(15:1)); in _mhal_mhl_ECbusInitialSetting()
1438 W2BYTEMSK(REG_MHL_ECBUS_PHY_4E, 0x001C, BMASK(15:0)); in _mhal_mhl_ECbusInitialSetting()
1439 W2BYTEMSK(REG_MHL_ECBUS_PHY_51, 0x0100, BMASK(15:0)); in _mhal_mhl_ECbusInitialSetting()
1440 W2BYTEMSK(REG_MHL_ECBUS_PHY_56, 0x0200, BMASK(15:0)); in _mhal_mhl_ECbusInitialSetting()
1441 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BMASK(14:13), BMASK(14:13)); // [14:13] in _mhal_mhl_ECbusInitialSetting()
1442 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusInitialSetting()
1443 W2BYTEMSK(REG_MHL_ECBUS_PHY_55, 0, BMASK(15:4)); //[7:0] in _mhal_mhl_ECbusInitialSetting()
1444 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, 0x00F0, BMASK(15:0)); // [7:4]:reg_ecbss_afe_tx_dri_step in _mhal_mhl_ECbusInitialSetting()
1445 W2BYTEMSK(REG_MHL_ECBUS_PHY_78, BIT(0), BIT(0)); in _mhal_mhl_ECbusInitialSetting()
1447 W2BYTEMSK(REG_MHL_ECBUS_0E, 8, BMASK(4:0)); in _mhal_mhl_ECbusInitialSetting()
1448 W2BYTEMSK(REG_MHL_ECBUS_2D, BIT(3), BIT(3)); in _mhal_mhl_ECbusInitialSetting()
1451 W2BYTEMSK(REG_MHL_ECBUS_PHY_7F, BIT(2), BIT(2)); // [2]:reg_rst_aft_clklck_en in _mhal_mhl_ECbusInitialSetting()
1452 …W2BYTEMSK(REG_MHL_ECBUS_00, BMASK(4:3), BMASK(4:3)); // [4]:reg_rst_aft_fail_en, [3]:reg_rst_aft_c… in _mhal_mhl_ECbusInitialSetting()
1455 W2BYTEMSK(REG_MHL_ECBUS_02, BIT(7), BMASK(13:8)| BIT(7)); // [7] in _mhal_mhl_ECbusInitialSetting()
1456 W2BYTEMSK(REG_MHL_ECBUS_PHY_6D, BIT(5), BMASK(6:5)); in _mhal_mhl_ECbusInitialSetting()
1457 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, 0x06, BMASK(3:0)); // [11:8]: in _mhal_mhl_ECbusInitialSetting()
1458 W2BYTEMSK(REG_MHL_ECBUS_PHY_68, 0x30, BMASK(6:4)); // [6:4]: pre-deglitch in _mhal_mhl_ECbusInitialSetting()
1459 …W2BYTEMSK(REG_MHL_ECBUS_PHY_69, 0x50, BMASK(6:4)| BMASK(2:0)); // [6:4]: rasing pattern type, [2:0… in _mhal_mhl_ECbusInitialSetting()
1460 …W2BYTEMSK(REG_MHL_ECBUS_PHY_65, 0x08, BMASK(5:0)); // [5:0]: reg_dat_lsb_mask; after analog rwa da… in _mhal_mhl_ECbusInitialSetting()
1463 …W2BYTEMSK(REG_MHL_ECBUS_77, (_mhal_mhl_GetEMSCOneByteCRC(5) << 8)| _mhal_mhl_GetEMSCOneByteCRC(4),… in _mhal_mhl_ECbusInitialSetting()
1464 …W2BYTEMSK(REG_MHL_ECBUS_78, (_mhal_mhl_GetEMSCOneByteCRC(7) << 8)| _mhal_mhl_GetEMSCOneByteCRC(6),… in _mhal_mhl_ECbusInitialSetting()
1465 …W2BYTEMSK(REG_MHL_ECBUS_79, BIT(11)| (_mhal_mhl_GetEMSCTwoByteCRC(1, 1) << 3)| (_mhal_mhl_GetEMSCT… in _mhal_mhl_ECbusInitialSetting()
1466 W2BYTEMSK(REG_MHL_ECBUS_PHY_13, BIT(4), BIT(4)); // in _mhal_mhl_ECbusInitialSetting()
1467 W2BYTEMSK(REG_MHL_ECBUS_PHY_51, BIT(11), BIT(11)); // in _mhal_mhl_ECbusInitialSetting()
1470 …W2BYTEMSK(REG_MHL_ECBUS_04, 0xE0E, BMASK(14:8)| BMASK(6:0)); // [14:8]: reg_t_sink_cal, [6:0]: reg… in _mhal_mhl_ECbusInitialSetting()
1471 W2BYTEMSK(REG_MHL_ECBUS_06, 0x1C00, BMASK(14:8)); // [14:8]: reg_t_snk_tdm; in _mhal_mhl_ECbusInitialSetting()
1472 …W2BYTEMSK(REG_MHL_ECBUS_03, BMASK(15:14), BMASK(15:14)); // [15]:reg_wait_tdm_timer_dis [14]:reg_w… in _mhal_mhl_ECbusInitialSetting()
1473 W2BYTEMSK(REG_MHL_ECBUS_07, 0x104, BMASK(14:8)| BMASK(6:0)); // [14:8]: reg_t_snk_tdm; in _mhal_mhl_ECbusInitialSetting()
1474 W2BYTEMSK(REG_MHL_ECBUS_3F, 0, BMASK(1:0)); // in _mhal_mhl_ECbusInitialSetting()
1475 W2BYTEMSK(REG_MHL_ECBUS_48, 0, BMASK(2:0)); // in _mhal_mhl_ECbusInitialSetting()
1478 …W2BYTEMSK(REG_MHL_ECBUS_PHY_70, 0x032B, BMASK(15:0)); // [15:0]:reg_crlock_mid; the CR lock refere… in _mhal_mhl_ECbusInitialSetting()
1479 …W2BYTEMSK(REG_MHL_ECBUS_PHY_71, 0x0C04, BMASK(15:0)); // [15:8]:reg_crlock_thr, the CR lock refere… in _mhal_mhl_ECbusInitialSetting()
1480 …W2BYTEMSK(REG_MHL_ECBUS_PHY_72, 0x0007, BMASK(15:0)); // [12:8]:reg_cr_unlock_num, clock unlock th… in _mhal_mhl_ECbusInitialSetting()
1484 …W2BYTEMSK(REG_MHL_ECBUS_PHY_5C, 0x010A, BMASK(15:0)); // [10:8]:reg_txloc_golden_lowr_tol, [5:0… in _mhal_mhl_ECbusInitialSetting()
1485 …W2BYTEMSK(REG_MHL_ECBUS_PHY_66, 0x2117, BMASK(15:0)); // [14:12]:reg_txloc_golden2_tol, [10:8]:re… in _mhal_mhl_ECbusInitialSetting()
1486 …W2BYTEMSK(REG_MHL_ECBUS_PHY_67, 0x0403, BMASK(15:0)); // [14:12]:reg_val_aft_adj_ok, [10:8]:reg_tx… in _mhal_mhl_ECbusInitialSetting()
1487 W2BYTEMSK(REG_MHL_ECBUS_PHY_69, BIT(10), BMASK(11:10)); // [11:10]:reg_txloc_set_time in _mhal_mhl_ECbusInitialSetting()
1488 …W2BYTEMSK(REG_MHL_ECBUS_PHY_6A, 0xf117, BMASK(15:0)); // [15:12]:reg_txloc_lck_thr, [10:8]:reg_txl… in _mhal_mhl_ECbusInitialSetting()
1492 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(8)| 0x33, BIT(8)| BMASK(7:4)); in _mhal_mhl_ECbusInitialSetting()
1495 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(8)| 0x00, BIT(8)| BMASK(7:4)); in _mhal_mhl_ECbusInitialSetting()
1498 W2BYTEMSK(REG_MHL_ECBUS_PHY_6D, BIT(8), BIT(8)); in _mhal_mhl_ECbusInitialSetting()
1500 W2BYTEMSK(REG_MHL_ECBUS_PHY_6C, 0x0000, BMASK(15:0)); in _mhal_mhl_ECbusInitialSetting()
1519 W2BYTEMSK(REG_MHL_ECBUS_36, 0, BIT(0)); // Ecbus state change int mask in _mhal_mhl_SetECbusStateChangeInterrupt()
1523 W2BYTEMSK(REG_MHL_ECBUS_36, BIT(0), BIT(0)); // Ecbus state change int mask in _mhal_mhl_SetECbusStateChangeInterrupt()
1526 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); // Ecbus state change int clear in _mhal_mhl_SetECbusStateChangeInterrupt()
1541 W2BYTEMSK(REG_MHL_ECBUS_36, bEnableFlag? 0: BIT(12), BIT(12)); // eMSC receive int mask in _mhal_mhl_SetEMSCReceiveInterrupt()
1542 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); // eMSC receive int clear in _mhal_mhl_SetEMSCReceiveInterrupt()
1557 …W2BYTEMSK(REG_PM_MHL_CBUS_0B, bEnableFlag? MHL_CBUS_CONNECT_CHECK_VALUE: 0, BMASK(15:0)); // [15:0… in _mhal_mhl_CbusConnectCheckEnable()
1572 W2BYTEMSK(REG_MHL_ECBUS_PHY_4D, bEnableFlag? 0: BIT(0), BIT(0)); // ECbus PLL pd in _mhal_mhl_ECbusEnableSetting()
1574 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, bEnableFlag? BIT(3): BIT(2), BMASK(3:2)); // in _mhal_mhl_ECbusEnableSetting()
1575 W2BYTEMSK(REG_MHL_ECBUS_PHY_6F, bEnableFlag? BIT(8): 0, BIT(8)); // ECbus clock detect in _mhal_mhl_ECbusEnableSetting()
1576 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, bEnableFlag? 0: BIT(13), BIT(13)); in _mhal_mhl_ECbusEnableSetting()
1577 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, bEnableFlag? 0: BIT(13), BIT(13)); in _mhal_mhl_ECbusEnableSetting()
1581 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(13), BIT(13)); // [13]: ECbus on in _mhal_mhl_ECbusEnableSetting()
1585 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(14), BIT(14)); // [14]: ECbus off in _mhal_mhl_ECbusEnableSetting()
1601 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, bEnableFlag? BIT(3): 0, BIT(3)); // [3]: Enable ECbus dmux in _mhal_mhl_ECbusDmuxEnable()
1616 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(0), BIT(0)); in _mhal_mhl_CbusEngineReset()
1617 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(0)); in _mhal_mhl_CbusEngineReset()
1632 W2BYTEMSK(REG_MHL_ECBUS_00, BMASK(1:0), BMASK(1:0)); // ECbus state reset in _mhal_mhl_ECbusStateReset()
1633 W2BYTEMSK(REG_MHL_ECBUS_00, 0, BMASK(1:0)); // ECbus state reset in _mhal_mhl_ECbusStateReset()
1648 …W2BYTEMSK(REG_MHL_CBUS_17, bECbusEnable? 0x7000: 0x0800, BMASK(15:8)); // [15:8]: reg_ddc_hdcp_sho… in _mhal_mhl_SetShortReadAddress()
1671 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_60_L, bEnableFlag? BMASK(10:8): 0, BMASK(10:8)); // [8]: MHL3 engin… in _mhal_mhl_Version3PhyEnable()
1672 …W2BYTEMSK(REG_COMBO_PHY0_P0_73_L, bEnableFlag? MHL_EQ_30_SETTING_VALUE: MHL_EQ_20_SETTING_VALUE, B… in _mhal_mhl_Version3PhyEnable()
1673 W2BYTEMSK(REG_COMBO_PHY0_P0_60_L, bEnableFlag? 0: BIT(5), BIT(5)); in _mhal_mhl_Version3PhyEnable()
1683 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_60_L, bEnableFlag? BMASK(10:8): 0, BMASK(10:8)); // [8]: MHL3 engin… in _mhal_mhl_Version3PhyEnable()
1684 …W2BYTEMSK(REG_COMBO_PHY0_P1_73_L, bEnableFlag? MHL_EQ_30_SETTING_VALUE: MHL_EQ_20_SETTING_VALUE, B… in _mhal_mhl_Version3PhyEnable()
1685 W2BYTEMSK(REG_COMBO_PHY0_P1_60_L, bEnableFlag? 0: BIT(5), BIT(5)); in _mhal_mhl_Version3PhyEnable()
1695 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_60_L, bEnableFlag? BMASK(10:8): 0, BMASK(10:8)); // [8]: MHL3 engin… in _mhal_mhl_Version3PhyEnable()
1696 …W2BYTEMSK(REG_COMBO_PHY0_P2_73_L, bEnableFlag? MHL_EQ_30_SETTING_VALUE: MHL_EQ_20_SETTING_VALUE, B… in _mhal_mhl_Version3PhyEnable()
1697 W2BYTEMSK(REG_COMBO_PHY0_P2_60_L, bEnableFlag? 0: BIT(5), BIT(5)); in _mhal_mhl_Version3PhyEnable()
1707 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_60_L, bEnableFlag? BMASK(10:8): 0, BMASK(10:8)); // [8]: MHL3 engin… in _mhal_mhl_Version3PhyEnable()
1708 …W2BYTEMSK(REG_COMBO_PHY0_P3_73_L, bEnableFlag? MHL_EQ_30_SETTING_VALUE: MHL_EQ_20_SETTING_VALUE, B… in _mhal_mhl_Version3PhyEnable()
1709 W2BYTEMSK(REG_COMBO_PHY0_P3_60_L, bEnableFlag? 0: BIT(5), BIT(5)); in _mhal_mhl_Version3PhyEnable()
1748 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(4), BIT(4)); // [4] in _mhal_mhl_ECbusStateChangeProc()
1764 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(13), BIT(13));// in _mhal_mhl_ECbusStateChangeProc()
1768 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(13)| BIT(12), BMASK(14:12)); // delay in _mhal_mhl_ECbusStateChangeProc()
1792 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(4), BIT(4)); // [4]: clear PLL lock status in _mhal_mhl_ECbusModeUpProc()
1793 W2BYTEMSK(REG_MHL_ECBUS_34, 0, BIT(4)); // [4]: clear PLL lock status in _mhal_mhl_ECbusModeUpProc()
1797 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(13), BIT(13)); in _mhal_mhl_ECbusModeUpProc()
1798 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:12), BMASK(14:12)); // delay in _mhal_mhl_ECbusModeUpProc()
1815 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(13), BIT(13)); in _mhal_mhl_ECbusModeDownProc()
1830 …W2BYTEMSK(REG_HDMI2_DUAL_0_54_L, bLinkRate6GFlag? 0: BIT(1), BMASK(1:0)); // [1:0]: reg_avg_ctrl_c… in _mhal_mhl_MHL3MuxSetting0()
1845 W2BYTEMSK(REG_MHL_ECBUS_23, BIT(15), BIT(15)); in _mhal_mhl_GetSRAMReceiveEMSCData()
1864 W2BYTEMSK(REG_MHL_ECBUS_20, ucSendEMSC, BMASK(7:0)); in _mhal_mhl_InsertSRAMSendEMSCData()
1866 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(15), BIT(15)); in _mhal_mhl_InsertSRAMSendEMSCData()
2467 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_72_L, BIT(13), BIT(13)); in mhal_mhl_CDRModeMonitor()
2469 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_72_L, 0, BIT(13)); in mhal_mhl_CDRModeMonitor()
2528 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_72_L, BIT(13), BIT(13)); in mhal_mhl_CDRModeMonitor()
2530 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_72_L, 0, BIT(13)); in mhal_mhl_CDRModeMonitor()
2589 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_72_L, BIT(13), BIT(13)); in mhal_mhl_CDRModeMonitor()
2591 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_72_L, 0, BIT(13)); in mhal_mhl_CDRModeMonitor()
2650 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_72_L, BIT(13), BIT(13)); in mhal_mhl_CDRModeMonitor()
2652 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_72_L, 0, BIT(13)); in mhal_mhl_CDRModeMonitor()
2722 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
2726 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
2749 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
2753 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
2766 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
2770 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
2803 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0)); in mhal_mhl_VbusCharge()
2807 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
2811 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0)); in mhal_mhl_VbusCharge()
2834 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0)); in mhal_mhl_VbusCharge()
2838 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
2842 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0)); in mhal_mhl_VbusCharge()
2855 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0)); in mhal_mhl_VbusCharge()
2859 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
2863 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0)); in mhal_mhl_VbusCharge()
2890 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(5), BIT(5)); in mhal_mhl_CbusFloating()
2894 W2BYTEMSK(REG_PM_MHL_CBUS_17, 0, BIT(5)); in mhal_mhl_CbusFloating()
2912 W2BYTEMSK(REG_PM_MHL_CBUS_18, 0, BIT(1)); // cbus stuck to low int mask in mhal_mhl_CbusStucktoLow()
2916 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(1), BIT(1)); // cbus stuck to low int mask in mhal_mhl_CbusStucktoLow()
2919 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(0), BIT(0)); // Clear cbus stuck to low int flag in mhal_mhl_CbusStucktoLow()
2936 W2BYTEMSK(REG_PM_MHL_CBUS_18, 0, BIT(5)); // wake up pulse int mask in mhal_mhl_CbusWakeupInterrupt()
2940 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(5), BIT(5)); // wake up pulse int mask in mhal_mhl_CbusWakeupInterrupt()
2943 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(4), BIT(4)); // Clear wake up pulse int flag in mhal_mhl_CbusWakeupInterrupt()
2958 W2BYTEMSK(REG_MHL_CBUS_00, (ucVenderID << 8), BMASK(15:8)); in mhal_mhl_SetVenderID()
2980 W2BYTEMSK(REG_MHL_CBUS_52, BIT(1), BIT(1)); // CPU write enable in mhal_mhl_LoadEDID()
2984 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address in mhal_mhl_LoadEDID()
2985 W2BYTEMSK(REG_MHL_CBUS_53, edid[ustemp], 0x00FF); // data in mhal_mhl_LoadEDID()
2986 W2BYTEMSK(REG_MHL_CBUS_52, BIT(0), BIT(0)); // write trigger in mhal_mhl_LoadEDID()
2987 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_LoadEDID()
2991 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(1)); // CPU write disable in mhal_mhl_LoadEDID()
3016 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address in mhal_mhl_ReadEDID()
3017 W2BYTEMSK(REG_MHL_CBUS_52, BIT(3), BIT(3)); // read trigger in mhal_mhl_ReadEDID()
3018 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_ReadEDID()
3059 W2BYTEMSK(REG_MHL_CBUS_09, devcap[15], BMASK(7:0)); in mhal_mhl_LoadDeviceCapability()
3086 …W2BYTEMSK(tMHL_INITIAL_TABLE[uctemp].addr, tMHL_INITIAL_TABLE[uctemp].databuf, tMHL_INITIAL_TABLE[… in mhal_mhl_initial()
3092 …W2BYTEMSK(REG_PM_SLEEP_72_L, BMASK(7:6), BMASK(8:6)); // [8]: reg_cbus_debug_sel, [7]: reg_vbus_en… in mhal_mhl_initial()
3098 W2BYTEMSK(0x2B28, 0, BIT(11)); in mhal_mhl_initial()
3111 …W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4)|BIT(0), BIT(4)|BIT(1)|BIT(0)); // [1]: receive packet valid mask in mhal_mhl_initial()
3148 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11)); in mhal_mhl_InvertCableDetect()
3168 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11)); in mhal_mhl_InvertCableDetect()
3178 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11)); in mhal_mhl_InvertCableDetect()
3214 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3215 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3219 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3226 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3230 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3254 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3255 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3259 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3266 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3270 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3284 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3285 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3289 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3296 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3300 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3448 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(0), BIT(0)); in mhal_mhl_CbusIsMscMsgReceived()
3470 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(0), BIT(0)); in mhal_mhl_CbusStucktoLowFlag()
3492 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(4), BIT(4)); in mhal_mhl_CbusWakeupIntFlag()
3514 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); in mhal_mhl_GetECbusStateChangeFlag()
3538 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); in mhal_mhl_GetEMSCReceiveFlag()
3560 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(10), BIT(10)); // eMSC send pass clear in mhal_mhl_GetEMSCSendStatus()
3566 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(9), BIT(9)); // eMSC send fail clear in mhal_mhl_GetEMSCSendStatus()
3601 W2BYTEMSK(REG_MHL_CBUS_25, BIT(12), BIT(12)); // trigger to send in mhal_mhl_CBusWrite()
3636 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(12), BIT(12)); in mhal_mhl_Cbus_SetPathEn()
3640 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(13), BIT(13)); in mhal_mhl_Cbus_SetPathEn()
3704 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in mhal_mhl_CbusIntCB()
4000 …W2BYTEMSK(tMHL_POWER_ON_TABLE[uctemp].addr, tMHL_POWER_ON_TABLE[uctemp].databuf, tMHL_POWER_ON_TAB… in mhal_mhl_LoadPowerOnTbl()
4017 …W2BYTEMSK(tMHL_POWER_SAVING_TABLE[uctemp].addr, tMHL_POWER_SAVING_TABLE[uctemp].databuf, tMHL_POWE… in mhal_mhl_LoadPowerStandbyTbl()
4035 …W2BYTEMSK(tMHL_POWER_DOWN_TABLE[uctemp].addr, tMHL_POWER_DOWN_TABLE[uctemp].databuf, tMHL_POWER_DO… in mhal_mhl_LoadPowerDownTbl()
4058 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(3), BMASK(4:3)); // [4]: output val, [3]: oen in mhal_mhl_SetHPD()
4063 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(4:3)); // [4]: output val, [3]: oen in mhal_mhl_SetHPD()
4111 W2BYTEMSK(REG_MHL_CBUS_10, BIT(15), BIT(15)); in mhal_mhl_GetSRAMReceiveData()
4135 W2BYTEMSK(0x001106, BIT(10), BIT(10)); in mhal_mhl_TestSignal()
4139 W2BYTEMSK(0x001106, 0, BIT(10)); in mhal_mhl_TestSignal()
4176 …W2BYTEMSK(REG_COMBO_PHY1_P0_0D_L, (ucLinkRate << 12), BMASK(13:12)); // [13:12]: Select MHL3 data … in mhal_mhl_SetMainLinkRate()
4195 …W2BYTEMSK(REG_COMBO_PHY1_P1_0D_L, (ucLinkRate << 12), BMASK(13:12)); // [13:12]: Select MHL3 data … in mhal_mhl_SetMainLinkRate()
4214 …W2BYTEMSK(REG_COMBO_PHY1_P2_0D_L, (ucLinkRate << 12), BMASK(13:12)); // [13:12]: Select MHL3 data … in mhal_mhl_SetMainLinkRate()
4233 …W2BYTEMSK(REG_COMBO_PHY1_P3_0D_L, (ucLinkRate << 12), BMASK(13:12)); // [13:12]: Select MHL3 data … in mhal_mhl_SetMainLinkRate()
4276 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, 0, BIT(13)); in mhal_mhl_GetECbusStatusFlag()
4429 W2BYTEMSK(REG_MHL_ECBUS_1C, usEMSCFreeBuffer, BMASK(9:0)); in mhal_mhl_GetEMSCReceiveData()
4430 W2BYTEMSK(REG_MHL_ECBUS_1C, BIT(15), BIT(15)); in mhal_mhl_GetEMSCReceiveData()
4450 W2BYTEMSK(REG_MHL_ECBUS_1B, (ucLength -1), BMASK(9:0)); // Request command byte count in mhal_mhl_InsertEMSCSendData()
4451 …W2BYTEMSK(REG_MHL_ECBUS_79, _mhal_mhl_GetEMSCTwoByteCRC(0, (ucLength -1)) , BMASK(2:0)); // byte c… in mhal_mhl_InsertEMSCSendData()
4453 W2BYTEMSK(REG_MHL_ECBUS_21, 0, BMASK(9:0)); // SRAM address set 0 in mhal_mhl_InsertEMSCSendData()
4454 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(13), BIT(13)); // Trigger address in mhal_mhl_InsertEMSCSendData()
4465 W2BYTEMSK(REG_MHL_ECBUS_19, BIT(15), BIT(15)); // eMSC payload CRC ove in mhal_mhl_InsertEMSCSendData()
4470 W2BYTEMSK(REG_MHL_ECBUS_1B, BIT(15), BIT(15)); // REG_MHL_ECBUS2_1B[15] in mhal_mhl_InsertEMSCSendData()