Searched refs:TSP_HWINT3_STATUS_MASK (Results 1 – 9 of 9) sorted by relevance
3764 (REG16_R(&_RegCtrl->HwInt3_Stat) & (~TSP_HWINT3_STATUS_MASK)) | in HAL_TSP_PcrFlt_ClearInt()3765 (~TSP_HWINT3_PCR2_UPDATE_END & TSP_HWINT3_STATUS_MASK)); in HAL_TSP_PcrFlt_ClearInt()3770 (REG16_R(&_RegCtrl->HwInt3_Stat) & (~TSP_HWINT3_STATUS_MASK)) | in HAL_TSP_PcrFlt_ClearInt()3771 (~TSP_HWINT3_PCR3_UPDATE_END & TSP_HWINT3_STATUS_MASK)); in HAL_TSP_PcrFlt_ClearInt()6224 …REG16_SET(&_RegCtrl->HwInt3_Stat, (TSP_HWINT3_EN_MASK & (u32Mask >> 16)) | TSP_HWINT3_STATUS_MASK); in HAL_TSP_INT_Enable()6241 …G16_R(&_RegCtrl->HwInt3_Stat) & ~(TSP_HWINT3_EN_MASK & (u32Mask >> 16))) | TSP_HWINT3_STATUS_MASK); in HAL_TSP_INT_Disable()6260 (REG16_R(&_RegCtrl->HwInt3_Stat) & (~TSP_HWINT3_STATUS_MASK)) | in HAL_TSP_INT_ClrHW()6261 (((~(u32Mask >> 16))<< TSP_HWINT3_STATUS_SHIFT) & TSP_HWINT3_STATUS_MASK) ); in HAL_TSP_INT_ClrHW()6269 …status = (MS_U32)(((REG16_R(&_RegCtrl->HwInt3_Stat) & TSP_HWINT3_STATUS_MASK) >> TSP_HWINT3_STATUS… in HAL_TSP_INT_GetHW()
1211 #define TSP_HWINT3_STATUS_MASK 0xFF00 macro
3912 (REG16_R(&_RegCtrl->HwInt3_Stat) & (~TSP_HWINT3_STATUS_MASK)) | in HAL_TSP_PcrFlt_ClearInt()3913 (~TSP_HWINT3_PCR2_UPDATE_END & TSP_HWINT3_STATUS_MASK)); in HAL_TSP_PcrFlt_ClearInt()3918 (REG16_R(&_RegCtrl->HwInt3_Stat) & (~TSP_HWINT3_STATUS_MASK)) | in HAL_TSP_PcrFlt_ClearInt()3919 (~TSP_HWINT3_PCR3_UPDATE_END & TSP_HWINT3_STATUS_MASK)); in HAL_TSP_PcrFlt_ClearInt()6595 …REG16_SET(&_RegCtrl->HwInt3_Stat, (TSP_HWINT3_EN_MASK & (u32Mask >> 16)) | TSP_HWINT3_STATUS_MASK); in HAL_TSP_INT_Enable()6615 TSP_HWINT3_STATUS_MASK); in HAL_TSP_INT_Disable()6634 (REG16_R(&_RegCtrl->HwInt3_Stat) & (~TSP_HWINT3_STATUS_MASK)) | in HAL_TSP_INT_ClrHW()6635 (((~(u32Mask >> 16))<< TSP_HWINT3_STATUS_SHIFT) & TSP_HWINT3_STATUS_MASK) ); in HAL_TSP_INT_ClrHW()6643 …status = (MS_U32)(((REG16_R(&_RegCtrl->HwInt3_Stat) & TSP_HWINT3_STATUS_MASK) >> TSP_HWINT3_STATUS… in HAL_TSP_INT_GetHW()
1246 #define TSP_HWINT3_STATUS_MASK 0xFF00 macro
1242 #define TSP_HWINT3_STATUS_MASK 0xFF00 macro
4385 …T(&_RegCtrl->HwInt3_Stat, (((u32Mask >> 16) << TSP_HWINT3_STATUS_SHIFT) & TSP_HWINT3_STATUS_MASK)); in HAL_TSP_INT_ClrHW()4386 …R(&_RegCtrl->HwInt3_Stat, (((u32Mask >> 16) << TSP_HWINT3_STATUS_SHIFT) & TSP_HWINT3_STATUS_MASK)); in HAL_TSP_INT_ClrHW()4394 …status = (MS_U32)(((REG16_R(&_RegCtrl->HwInt3_Stat) & TSP_HWINT3_STATUS_MASK) >> TSP_HWINT3_STATUS… in HAL_TSP_INT_GetHW()
1244 #define TSP_HWINT3_STATUS_MASK 0xFF00 macro