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Searched refs:TDF_REG_BASE (Results 1 – 25 of 46) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7621/demod/
H A DhalDMD_INTERN_common.c438 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x22, 0x03); in HAL_DMD_IFAGC_RegRead()
439 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x05, &reg_frz); in HAL_DMD_IFAGC_RegRead()
440 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz | 0x80); in HAL_DMD_IFAGC_RegRead()
441 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x25, &reg_tmp); in HAL_DMD_IFAGC_RegRead()
443 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x24, &reg_tmp); in HAL_DMD_IFAGC_RegRead()
445 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz); in HAL_DMD_IFAGC_RegRead()
455 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x22, 0x00); in HAL_DMD_IFAGC_RegRead()
456 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x05, &reg_frz); in HAL_DMD_IFAGC_RegRead()
457 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz | 0x80); in HAL_DMD_IFAGC_RegRead()
460 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x25, &reg_tmp); in HAL_DMD_IFAGC_RegRead()
[all …]
H A DhalDMD_INTERN_DVBC.c1421 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03); in INTERN_DVBC_GetLock()
1422 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, &reg_frz); in INTERN_DVBC_GetLock()
1423 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80); in INTERN_DVBC_GetLock()
1424 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &cData); in INTERN_DVBC_GetLock()
1425 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz); in INTERN_DVBC_GetLock()
1945 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5b, &reg); in INTERN_DVBC_Get_FreqOffset()
1947 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5a, &reg); in INTERN_DVBC_Get_FreqOffset()
1949 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x59, &reg); in INTERN_DVBC_Get_FreqOffset()
1951 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x58, &reg); in INTERN_DVBC_Get_FreqOffset()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/manhattan/demod/
H A DhalDMD_INTERN_common.c437 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x22, 0x03); in HAL_DMD_IFAGC_RegRead()
438 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x04, &reg_frz); in HAL_DMD_IFAGC_RegRead()
439 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x04, reg_frz | 0x80); in HAL_DMD_IFAGC_RegRead()
440 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x25, &reg_tmp); in HAL_DMD_IFAGC_RegRead()
442 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x24, &reg_tmp); in HAL_DMD_IFAGC_RegRead()
444 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x04, reg_frz); in HAL_DMD_IFAGC_RegRead()
454 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x22, 0x00); in HAL_DMD_IFAGC_RegRead()
455 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x04, &reg_frz); in HAL_DMD_IFAGC_RegRead()
456 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x04, reg_frz | 0x80); in HAL_DMD_IFAGC_RegRead()
459 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x25, &reg_tmp); in HAL_DMD_IFAGC_RegRead()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6lite/demod/
H A DhalDMD_INTERN_common.c438 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x22, 0x03); in HAL_DMD_IFAGC_RegRead()
439 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x05, &reg_frz); in HAL_DMD_IFAGC_RegRead()
440 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz | 0x80); in HAL_DMD_IFAGC_RegRead()
441 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x25, &reg_tmp); in HAL_DMD_IFAGC_RegRead()
443 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x24, &reg_tmp); in HAL_DMD_IFAGC_RegRead()
445 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz); in HAL_DMD_IFAGC_RegRead()
455 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x22, 0x00); in HAL_DMD_IFAGC_RegRead()
456 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x05, &reg_frz); in HAL_DMD_IFAGC_RegRead()
457 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz | 0x80); in HAL_DMD_IFAGC_RegRead()
460 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x25, &reg_tmp); in HAL_DMD_IFAGC_RegRead()
[all …]
H A DhalDMD_INTERN_DVBC.c2789 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03); in INTERN_DVBC_GetLock()
2790 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, &reg_frz); in INTERN_DVBC_GetLock()
2791 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80); in INTERN_DVBC_GetLock()
2792 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &cData); in INTERN_DVBC_GetLock()
2793 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz); in INTERN_DVBC_GetLock()
3001 …status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE+BANK_BASE_OFFSET*hal_demod_swtich_status + 0x2… in INTERN_DVBC_GetIFAGC()
3002 …status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE +BANK_BASE_OFFSET*hal_demod_swtich_status +0x05… in INTERN_DVBC_GetIFAGC()
3003 …status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE +BANK_BASE_OFFSET*hal_demod_swtich_status +0x0… in INTERN_DVBC_GetIFAGC()
3004 …status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE +BANK_BASE_OFFSET*hal_demod_swtich_status+ 0x25… in INTERN_DVBC_GetIFAGC()
3006 …status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + BANK_BASE_OFFSET*hal_demod_swtich_status+0x24… in INTERN_DVBC_GetIFAGC()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6/demod/
H A DhalDMD_INTERN_common.c438 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x22, 0x03); in HAL_DMD_IFAGC_RegRead()
439 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x05, &reg_frz); in HAL_DMD_IFAGC_RegRead()
440 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz | 0x80); in HAL_DMD_IFAGC_RegRead()
441 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x25, &reg_tmp); in HAL_DMD_IFAGC_RegRead()
443 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x24, &reg_tmp); in HAL_DMD_IFAGC_RegRead()
445 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz); in HAL_DMD_IFAGC_RegRead()
455 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x22, 0x00); in HAL_DMD_IFAGC_RegRead()
456 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x05, &reg_frz); in HAL_DMD_IFAGC_RegRead()
457 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz | 0x80); in HAL_DMD_IFAGC_RegRead()
460 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x25, &reg_tmp); in HAL_DMD_IFAGC_RegRead()
[all …]
H A DhalDMD_INTERN_DVBC.c1371 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03); in INTERN_DVBC_GetLock()
1372 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, &reg_frz); in INTERN_DVBC_GetLock()
1373 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80); in INTERN_DVBC_GetLock()
1374 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &cData); in INTERN_DVBC_GetLock()
1375 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz); in INTERN_DVBC_GetLock()
1895 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5b, &reg); in INTERN_DVBC_Get_FreqOffset()
1897 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5a, &reg); in INTERN_DVBC_Get_FreqOffset()
1899 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x59, &reg); in INTERN_DVBC_Get_FreqOffset()
1901 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x58, &reg); in INTERN_DVBC_Get_FreqOffset()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maxim/demod/
H A DhalDMD_INTERN_common.c439 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x22, 0x03); in HAL_DMD_IFAGC_RegRead()
440 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x05, &reg_frz); in HAL_DMD_IFAGC_RegRead()
441 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz | 0x80); in HAL_DMD_IFAGC_RegRead()
442 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x25, &reg_tmp); in HAL_DMD_IFAGC_RegRead()
444 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x24, &reg_tmp); in HAL_DMD_IFAGC_RegRead()
446 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz); in HAL_DMD_IFAGC_RegRead()
456 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x22, 0x00); in HAL_DMD_IFAGC_RegRead()
457 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x05, &reg_frz); in HAL_DMD_IFAGC_RegRead()
458 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz | 0x80); in HAL_DMD_IFAGC_RegRead()
461 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x25, &reg_tmp); in HAL_DMD_IFAGC_RegRead()
[all …]
H A DhalDMD_INTERN_DVBC.c1421 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03); in INTERN_DVBC_GetLock()
1422 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, &reg_frz); in INTERN_DVBC_GetLock()
1423 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80); in INTERN_DVBC_GetLock()
1424 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &cData); in INTERN_DVBC_GetLock()
1425 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz); in INTERN_DVBC_GetLock()
1945 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5b, &reg); in INTERN_DVBC_Get_FreqOffset()
1947 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5a, &reg); in INTERN_DVBC_Get_FreqOffset()
1949 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x59, &reg); in INTERN_DVBC_Get_FreqOffset()
1951 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x58, &reg); in INTERN_DVBC_Get_FreqOffset()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maserati/demod/
H A DhalDMD_INTERN_common.c438 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x22, 0x03); in HAL_DMD_IFAGC_RegRead()
439 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x05, &reg_frz); in HAL_DMD_IFAGC_RegRead()
440 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz | 0x80); in HAL_DMD_IFAGC_RegRead()
441 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x25, &reg_tmp); in HAL_DMD_IFAGC_RegRead()
443 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x24, &reg_tmp); in HAL_DMD_IFAGC_RegRead()
445 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz); in HAL_DMD_IFAGC_RegRead()
455 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x22, 0x00); in HAL_DMD_IFAGC_RegRead()
456 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x05, &reg_frz); in HAL_DMD_IFAGC_RegRead()
457 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz | 0x80); in HAL_DMD_IFAGC_RegRead()
460 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x25, &reg_tmp); in HAL_DMD_IFAGC_RegRead()
[all …]
H A DhalDMD_INTERN_DVBC.c1371 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03); in INTERN_DVBC_GetLock()
1372 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, &reg_frz); in INTERN_DVBC_GetLock()
1373 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80); in INTERN_DVBC_GetLock()
1374 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &cData); in INTERN_DVBC_GetLock()
1375 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz); in INTERN_DVBC_GetLock()
1895 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5b, &reg); in INTERN_DVBC_Get_FreqOffset()
1897 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5a, &reg); in INTERN_DVBC_Get_FreqOffset()
1899 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x59, &reg); in INTERN_DVBC_Get_FreqOffset()
1901 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x58, &reg); in INTERN_DVBC_Get_FreqOffset()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/curry/demod/
H A DhalDMD_INTERN_common.c438 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x22, 0x03); in HAL_DMD_IFAGC_RegRead()
439 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x05, &reg_frz); in HAL_DMD_IFAGC_RegRead()
440 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz | 0x80); in HAL_DMD_IFAGC_RegRead()
441 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x25, &reg_tmp); in HAL_DMD_IFAGC_RegRead()
443 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x24, &reg_tmp); in HAL_DMD_IFAGC_RegRead()
445 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz); in HAL_DMD_IFAGC_RegRead()
455 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x22, 0x00); in HAL_DMD_IFAGC_RegRead()
456 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x05, &reg_frz); in HAL_DMD_IFAGC_RegRead()
457 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz | 0x80); in HAL_DMD_IFAGC_RegRead()
460 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x25, &reg_tmp); in HAL_DMD_IFAGC_RegRead()
[all …]
H A DhalDMD_INTERN_DVBC.c1371 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03); in INTERN_DVBC_GetLock()
1372 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, &reg_frz); in INTERN_DVBC_GetLock()
1373 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80); in INTERN_DVBC_GetLock()
1374 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &cData); in INTERN_DVBC_GetLock()
1375 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz); in INTERN_DVBC_GetLock()
1895 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5b, &reg); in INTERN_DVBC_Get_FreqOffset()
1897 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5a, &reg); in INTERN_DVBC_Get_FreqOffset()
1899 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x59, &reg); in INTERN_DVBC_Get_FreqOffset()
1901 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x58, &reg); in INTERN_DVBC_Get_FreqOffset()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7821/demod/
H A DhalDMD_INTERN_common.c438 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x22, 0x03); in HAL_DMD_IFAGC_RegRead()
439 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x05, &reg_frz); in HAL_DMD_IFAGC_RegRead()
440 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz | 0x80); in HAL_DMD_IFAGC_RegRead()
441 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x25, &reg_tmp); in HAL_DMD_IFAGC_RegRead()
443 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x24, &reg_tmp); in HAL_DMD_IFAGC_RegRead()
445 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz); in HAL_DMD_IFAGC_RegRead()
455 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x22, 0x00); in HAL_DMD_IFAGC_RegRead()
456 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x05, &reg_frz); in HAL_DMD_IFAGC_RegRead()
457 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz | 0x80); in HAL_DMD_IFAGC_RegRead()
460 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x25, &reg_tmp); in HAL_DMD_IFAGC_RegRead()
[all …]
H A DhalDMD_INTERN_DVBC.c1371 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03); in INTERN_DVBC_GetLock()
1372 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, &reg_frz); in INTERN_DVBC_GetLock()
1373 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80); in INTERN_DVBC_GetLock()
1374 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &cData); in INTERN_DVBC_GetLock()
1375 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz); in INTERN_DVBC_GetLock()
1895 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5b, &reg); in INTERN_DVBC_Get_FreqOffset()
1897 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5a, &reg); in INTERN_DVBC_Get_FreqOffset()
1899 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x59, &reg); in INTERN_DVBC_Get_FreqOffset()
1901 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x58, &reg); in INTERN_DVBC_Get_FreqOffset()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/kano/demod/
H A DhalDMD_INTERN_common.c438 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x22, 0x03); in HAL_DMD_IFAGC_RegRead()
439 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x05, &reg_frz); in HAL_DMD_IFAGC_RegRead()
440 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz | 0x80); in HAL_DMD_IFAGC_RegRead()
441 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x25, &reg_tmp); in HAL_DMD_IFAGC_RegRead()
443 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x24, &reg_tmp); in HAL_DMD_IFAGC_RegRead()
445 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz); in HAL_DMD_IFAGC_RegRead()
455 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x22, 0x00); in HAL_DMD_IFAGC_RegRead()
456 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x05, &reg_frz); in HAL_DMD_IFAGC_RegRead()
457 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x05, reg_frz | 0x80); in HAL_DMD_IFAGC_RegRead()
460 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x25, &reg_tmp); in HAL_DMD_IFAGC_RegRead()
[all …]
H A DhalDMD_INTERN_DVBC.c1371 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03); in INTERN_DVBC_GetLock()
1372 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, &reg_frz); in INTERN_DVBC_GetLock()
1373 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80); in INTERN_DVBC_GetLock()
1374 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &cData); in INTERN_DVBC_GetLock()
1375 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz); in INTERN_DVBC_GetLock()
1895 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5b, &reg); in INTERN_DVBC_Get_FreqOffset()
1897 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5a, &reg); in INTERN_DVBC_Get_FreqOffset()
1899 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x59, &reg); in INTERN_DVBC_Get_FreqOffset()
1901 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x58, &reg); in INTERN_DVBC_Get_FreqOffset()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/macan/demod/
H A DhalDMD_INTERN_common.c518 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03); in HAL_DMD_GetRFLevel()
519 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, &reg_frz); in HAL_DMD_GetRFLevel()
520 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80); in HAL_DMD_GetRFLevel()
521 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &reg_tmp); in HAL_DMD_GetRFLevel()
523 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x18, &reg_tmp); in HAL_DMD_GetRFLevel()
525 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz); in HAL_DMD_GetRFLevel()
600 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x00); in HAL_DMD_GetRFLevel()
601 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, &reg_frz); in HAL_DMD_GetRFLevel()
602 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80); in HAL_DMD_GetRFLevel()
613 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &reg_tmp); in HAL_DMD_GetRFLevel()
[all …]
H A DhalDMD_INTERN_DVBC.c1318 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03); in INTERN_DVBC_GetLock()
1319 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, &reg_frz); in INTERN_DVBC_GetLock()
1320 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80); in INTERN_DVBC_GetLock()
1321 MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &cData); in INTERN_DVBC_GetLock()
1322 MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz); in INTERN_DVBC_GetLock()
1823 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5b, &reg); in INTERN_DVBC_Get_FreqOffset()
1825 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x5a, &reg); in INTERN_DVBC_Get_FreqOffset()
1827 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x59, &reg); in INTERN_DVBC_Get_FreqOffset()
1829 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x58, &reg); in INTERN_DVBC_Get_FreqOffset()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/messi/demod/
H A DhalDMD_INTERN_common.c518 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03); in HAL_DMD_GetRFLevel()
519 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, &reg_frz); in HAL_DMD_GetRFLevel()
520 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80); in HAL_DMD_GetRFLevel()
521 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &reg_tmp); in HAL_DMD_GetRFLevel()
523 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x18, &reg_tmp); in HAL_DMD_GetRFLevel()
525 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz); in HAL_DMD_GetRFLevel()
600 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x00); in HAL_DMD_GetRFLevel()
601 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, &reg_frz); in HAL_DMD_GetRFLevel()
602 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80); in HAL_DMD_GetRFLevel()
613 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &reg_tmp); in HAL_DMD_GetRFLevel()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mainz/demod/
H A DhalDMD_INTERN_common.c518 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03); in HAL_DMD_GetRFLevel()
519 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, &reg_frz); in HAL_DMD_GetRFLevel()
520 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80); in HAL_DMD_GetRFLevel()
521 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &reg_tmp); in HAL_DMD_GetRFLevel()
523 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x18, &reg_tmp); in HAL_DMD_GetRFLevel()
525 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz); in HAL_DMD_GetRFLevel()
600 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x00); in HAL_DMD_GetRFLevel()
601 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, &reg_frz); in HAL_DMD_GetRFLevel()
602 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80); in HAL_DMD_GetRFLevel()
613 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &reg_tmp); in HAL_DMD_GetRFLevel()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maldives/demod/
H A DhalDMD_INTERN_common.c518 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03); in HAL_DMD_GetRFLevel()
519 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, &reg_frz); in HAL_DMD_GetRFLevel()
520 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80); in HAL_DMD_GetRFLevel()
521 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &reg_tmp); in HAL_DMD_GetRFLevel()
523 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x18, &reg_tmp); in HAL_DMD_GetRFLevel()
525 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz); in HAL_DMD_GetRFLevel()
600 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x00); in HAL_DMD_GetRFLevel()
601 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, &reg_frz); in HAL_DMD_GetRFLevel()
602 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80); in HAL_DMD_GetRFLevel()
613 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &reg_tmp); in HAL_DMD_GetRFLevel()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mustang/demod/
H A DhalDMD_INTERN_common.c518 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03); in HAL_DMD_GetRFLevel()
519 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, &reg_frz); in HAL_DMD_GetRFLevel()
520 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80); in HAL_DMD_GetRFLevel()
521 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &reg_tmp); in HAL_DMD_GetRFLevel()
523 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x18, &reg_tmp); in HAL_DMD_GetRFLevel()
525 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz); in HAL_DMD_GetRFLevel()
600 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x00); in HAL_DMD_GetRFLevel()
601 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, &reg_frz); in HAL_DMD_GetRFLevel()
602 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80); in HAL_DMD_GetRFLevel()
613 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &reg_tmp); in HAL_DMD_GetRFLevel()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mooney/demod/
H A DhalDMD_INTERN_common.c518 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03); in HAL_DMD_GetRFLevel()
519 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, &reg_frz); in HAL_DMD_GetRFLevel()
520 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80); in HAL_DMD_GetRFLevel()
521 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &reg_tmp); in HAL_DMD_GetRFLevel()
523 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x18, &reg_tmp); in HAL_DMD_GetRFLevel()
525 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz); in HAL_DMD_GetRFLevel()
600 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x00); in HAL_DMD_GetRFLevel()
601 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, &reg_frz); in HAL_DMD_GetRFLevel()
602 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80); in HAL_DMD_GetRFLevel()
613 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, &reg_tmp); in HAL_DMD_GetRFLevel()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/drv/dvb_extdemod/
H A DdrvDMD_EXTERN_MSB201X.c158 #define TDF_REG_BASE 0x2700 macro
3116 status &= _MDrv_DMD_MSB201X_SetReg(devID, TDF_REG_BASE + 0x16, 0x03); in _MDrv_DMD_MSB201X_GetRFLevel()
3117 status &= _MDrv_DMD_MSB201X_GetReg(devID, TDF_REG_BASE + 0x03, &reg_frz); in _MDrv_DMD_MSB201X_GetRFLevel()
3118 status &= _MDrv_DMD_MSB201X_SetReg(devID, TDF_REG_BASE + 0x03, reg_frz | 0x80); in _MDrv_DMD_MSB201X_GetRFLevel()
3119 status &= _MDrv_DMD_MSB201X_GetReg(devID, TDF_REG_BASE + 0x19, &reg_tmp); in _MDrv_DMD_MSB201X_GetRFLevel()
3121 status &= _MDrv_DMD_MSB201X_GetReg(devID, TDF_REG_BASE + 0x18, &reg_tmp); in _MDrv_DMD_MSB201X_GetRFLevel()
3123 status &= _MDrv_DMD_MSB201X_SetReg(devID, TDF_REG_BASE + 0x03, reg_frz); in _MDrv_DMD_MSB201X_GetRFLevel()
3204 … status &= _MDrv_DMD_MSB201X_SetReg(devID, TDF_REG_BASE + 0x16, 0x00); in _MDrv_DMD_MSB201X_GetRFLevel()
3205 status &= _MDrv_DMD_MSB201X_GetReg(devID, TDF_REG_BASE + 0x03, &reg_frz); in _MDrv_DMD_MSB201X_GetRFLevel()
3206 status &= _MDrv_DMD_MSB201X_SetReg(devID, TDF_REG_BASE + 0x03, reg_frz | 0x80); in _MDrv_DMD_MSB201X_GetRFLevel()
[all …]

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