1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2006-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // (��MStar Confidential Information��) by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102 #include "MsCommon.h"
103 #include "MsIRQ.h"
104 #include "MsOS.h"
105 #include "MsTypes.h"
106 #include "drvMMIO.h"
107 #include "drvDMD_common.h"
108 #include "drvDMD_VD_MBX.h"
109 #include "halDMD_INTERN_common.h"
110
111 #if defined (__aeon__) // Non-OS
112 #define BASEADDR_RIU 0xA0000000UL
113 //#elif ( OS_TYPE == linux ) // Linux
114 // #define RIU_BASE u32RegOSBase // MDrv_MIOMap_GetBASE(u32RegOSBase, puSize, MAP_NONPM_BANK)
115 #else // ecos
116 #define BASEADDR_RIU 0xBF800000UL
117 #endif
118
119 #define RIU_MACRO_START do {
120 #define RIU_MACRO_END } while (0)
121
122 // Address bus of RIU is 16 bits.
123 #define RIU_READ_BYTE(addr) ( READ_BYTE( _hal_DMD.virtDMDBaseAddr + (addr) ) )
124 #define RIU_READ_2BYTE(addr) ( READ_WORD( _hal_DMD.virtDMDBaseAddr + (addr) ) )
125 #define RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( _hal_DMD.virtDMDBaseAddr + (addr), val) }
126 #define RIU_WRITE_2BYTE(addr, val) { WRITE_WORD( _hal_DMD.virtDMDBaseAddr + (addr), val) }
127
128 //=============================================================
129 // Standard Form
130
131 #define RIU_ReadByte( u32Reg ) RIU_READ_BYTE(((u32Reg) << 1) - ((u32Reg) & 1))
132
133 #define RIU_Read2Byte( u32Reg ) (RIU_READ_2BYTE((u32Reg)<<1))
134
135 #define RIU_ReadRegBit( u32Reg, u8Mask ) (RIU_READ_BYTE(((u32Reg)<<1) - ((u32Reg) & 1)) & (u8Mask))
136
137 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \
138 RIU_MACRO_START \
139 RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) | (u8Mask)) : \
140 (RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) & ~(u8Mask))); \
141 RIU_MACRO_END
142
143 #define RIU_WriteByte( u32Reg, u8Val ) \
144 RIU_MACRO_START \
145 RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
146 RIU_MACRO_END
147
148 #define RIU_Write2Byte( u32Reg, u16Val ) \
149 RIU_MACRO_START \
150 if ( ((u32Reg) & 0x01) ) \
151 { \
152 RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
153 RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
154 } \
155 else \
156 { \
157 RIU_WRITE_2BYTE( ((u32Reg)<<1) , u16Val); \
158 } \
159 RIU_MACRO_END
160
161 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \
162 RIU_MACRO_START \
163 RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (RIU_READ_BYTE((((u32Reg) <<1) - ((u32Reg) & 1))) & ~(u8Msk)) | ((u8Val) & (u8Msk))); \
164 RIU_MACRO_END
165
166
167 typedef struct
168 {
169 MS_VIRT virtDMDBaseAddr;
170 MS_BOOL bBaseAddrInitialized;
171 } hal_DMD_t;
172
173 static hal_DMD_t _hal_DMD = // TODO: review, it would be init in Config()
174 {
175 .virtDMDBaseAddr = BASEADDR_RIU,
176 .bBaseAddrInitialized = 0,
177 };
178
179 extern s_I2C_Interface_func sI2cInterfaceFunc;
180
HAL_DMD_RegInit(void)181 MS_BOOL HAL_DMD_RegInit (void)
182 {
183 MS_VIRT virtNonPMBank;
184 MS_PHY phyNonPMBankSize;
185
186
187 printf("bryan check DMD init!!\n");
188 if (!MDrv_MMIO_GetBASE( &virtNonPMBank, &phyNonPMBankSize, MS_MODULE_PM))
189 {
190 #ifdef MS_DEBUG
191 printf("HAL_DMD_RegInit failure to get MS_MODULE_PM\n");
192 #endif
193 _hal_DMD.virtDMDBaseAddr = BASEADDR_RIU; // TODO what to do if failed??
194 _hal_DMD.bBaseAddrInitialized = 0;
195 return FALSE;
196 }
197
198 //HAL_ParFlash_Config(u32NonPMBank);
199 _hal_DMD.virtDMDBaseAddr=virtNonPMBank;
200 _hal_DMD.bBaseAddrInitialized = 1;
201 return TRUE;
202 }
203
HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)204 MS_U8 HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)
205 {
206 if (_hal_DMD.bBaseAddrInitialized)
207 {
208 return RIU_ReadByte(u32Addr);
209 }
210 else
211 {
212 #ifdef MS_DEBUG
213 printf("%s base address un-initialized\n", __FUNCTION__);
214 #endif
215 }
216 return 0;
217 }
218
HAL_DMD_RIU_ReadRegBit(MS_U32 u32Addr,MS_U8 u8Mask)219 MS_U8 HAL_DMD_RIU_ReadRegBit(MS_U32 u32Addr, MS_U8 u8Mask)
220 {
221 if (_hal_DMD.bBaseAddrInitialized)
222 {
223 return RIU_ReadRegBit(u32Addr, u8Mask);
224 }
225 else
226 {
227 #ifdef MS_DEBUG
228 printf("%s base address un-initialized\n", __FUNCTION__);
229 #endif
230 }
231 return 0;
232 }
HAL_DMD_IIC_ReadByte(MS_U16 u16SlaveAddr,MS_U32 u32Addr,MS_U8 * pu8Data)233 MS_U8 HAL_DMD_IIC_ReadByte(MS_U16 u16SlaveAddr, MS_U32 u32Addr, MS_U8 *pu8Data)
234 {
235
236 MS_BOOL bRet=TRUE;
237 MS_U8 u8MsbData[6] = {0};
238
239 u8MsbData[0] = 0x10;
240 u8MsbData[1] = 0x00;
241 u8MsbData[2] = 0x00;
242 u8MsbData[3] = (u32Addr >> 8) &0xff;
243 u8MsbData[4] = u32Addr &0xff;
244
245 u8MsbData[0] = 0x35;
246 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, u8MsbData);
247
248 u8MsbData[0] = 0x10;
249 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 5, u8MsbData);
250 bRet &= sI2cInterfaceFunc.I2C_ReadBytes(u16SlaveAddr, 0, 0, 1, pu8Data);
251
252 u8MsbData[0] = 0x34;
253 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, u8MsbData);
254
255 return bRet;
256 }
HAL_DMD_RIU_Read2Byte(MS_U32 u32Addr)257 MS_U16 HAL_DMD_RIU_Read2Byte(MS_U32 u32Addr)
258 {
259 if (_hal_DMD.bBaseAddrInitialized)
260 {
261 return RIU_Read2Byte(u32Addr);
262 }
263 else
264 {
265 #ifdef MS_DEBUG
266 printf("%s base address un-initialized\n", __FUNCTION__);
267 #endif
268 }
269 return 0;
270 }
271
HAL_DMD_IIC_WriteByte(MS_U16 u16SlaveAddr,MS_U32 u32Addr,MS_U8 u8Data)272 MS_U8 HAL_DMD_IIC_WriteByte(MS_U16 u16SlaveAddr, MS_U32 u32Addr, MS_U8 u8Data)
273 {
274 MS_BOOL bRet=TRUE;
275 MS_U8 u8MsbData[6] = {0};
276
277 u8MsbData[0] = 0x10;
278 u8MsbData[1] = 0x00;
279 u8MsbData[2] = 0x00;
280 u8MsbData[3] = (u32Addr >> 8) &0xff;
281 u8MsbData[4] = u32Addr &0xff;
282 u8MsbData[5] = u8Data;
283
284 u8MsbData[0] = 0x35;
285 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, u8MsbData);
286 u8MsbData[0] = 0x10;
287 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 6, u8MsbData);
288 u8MsbData[0] = 0x34;
289 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, u8MsbData);
290
291 return bRet;
292 }
HAL_DMD_IIC_WriteBytes(MS_U16 u16SlaveAddr,MS_U32 u32Addr,MS_U8 * u8Data,MS_U8 u8Len)293 MS_U8 HAL_DMD_IIC_WriteBytes(MS_U16 u16SlaveAddr, MS_U32 u32Addr, MS_U8 *u8Data, MS_U8 u8Len)
294 {
295 MS_BOOL bRet=TRUE;
296 MS_U16 index;
297 MS_U8 Data[0x80+5];
298
299 Data[0] = 0x10;
300 Data[1] = 0x00;
301 Data[2] = 0x00;
302 Data[3] = (u32Addr >> 8) &0xff;
303 Data[4] = u32Addr &0xff;
304
305 for(index = 0; index < u8Len ; index++)
306 {
307 Data[5+index] = u8Data[index];
308 }
309
310 Data[0] = 0x35;
311 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, Data);
312 Data[0] = 0x10;
313 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, Data);
314 sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, (5 + u8Len), Data);
315 Data[0] = 0x34;
316 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, Data);
317
318 return bRet;
319 }
320
HAL_DMD_I2C_Channel_Set(MS_U16 u16SlaveAddr,MS_U8 ch_num)321 MS_BOOL HAL_DMD_I2C_Channel_Set(MS_U16 u16SlaveAddr, MS_U8 ch_num)
322 {
323 MS_BOOL bRet=TRUE;
324 MS_U8 Data[5] = {0x53, 0x45, 0x52, 0x44, 0x42};
325 //Exit
326 Data[0] = 0x34;
327 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
328 Data[0]=(ch_num & 0x01)? 0x36 : 0x45;
329 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
330 //Init
331 Data[0] = 0x53;
332 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 5, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 5);
333 Data[0]=(ch_num & 0x04)? 0x80 : 0x81;
334 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
335 if ((ch_num==4)||(ch_num==5)||(ch_num==1))
336 Data[0]=0x82;
337 else
338 Data[0] = 0x83;
339 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
340
341 if ((ch_num==4)||(ch_num==5))
342 Data[0]=0x85;
343 else
344 Data[0] = 0x84;
345
346 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
347 Data[0]=(ch_num & 0x01)? 0x51 : 0x53;
348 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
349 Data[0]=(ch_num & 0x01)? 0x37 : 0x7F;
350 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
351 Data[0] = 0x35;
352 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
353 Data[0] = 0x71;
354 bRet &= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, NULL, 1, Data); //MDrv_msb131x_IIC_Write(DEMOD_MSB131X_SLAVE_ID, 0, 0, Data, 1);
355 // MsOS_ReleaseMutex(_s32MutexId);
356 return bRet;
357 }
358
HAL_DMD_I2C_Channel_Change(MS_U16 u16SlaveAddr,MS_U8 ch_num)359 MS_BOOL HAL_DMD_I2C_Channel_Change(MS_U16 u16SlaveAddr, MS_U8 ch_num)
360 {
361 MS_BOOL bRet=TRUE;
362 MS_U8 Data[5] = {0x53, 0x45, 0x52, 0x44, 0x42};
363 Data[0] = (ch_num & 0x01)? 0x81 : 0x80;
364 bRet&= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, Data);
365 Data[0] = (ch_num & 0x02)? 0x83 : 0x82;
366 bRet&= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, Data);
367 Data[0] = (ch_num & 0x04)? 0x85 : 0x84;
368 bRet&= sI2cInterfaceFunc.I2C_WriteBytes(u16SlaveAddr, 0, 0, 1, Data);
369
370 return bRet;
371 }
HAL_DMD_RIU_WriteByte(MS_U32 u32Addr,MS_U8 u8Value)372 void HAL_DMD_RIU_WriteByte(MS_U32 u32Addr, MS_U8 u8Value)
373 {
374 if (_hal_DMD.bBaseAddrInitialized)
375 {
376 RIU_WriteByte(u32Addr, u8Value);
377 }
378 else
379 {
380 #ifdef MS_DEBUG
381 printf("%s base address un-initialized\n", __FUNCTION__);
382 #endif
383 }
384 }
385
HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr,MS_BOOL bEnable,MS_U8 u8Mask)386 void HAL_DMD_RIU_WriteRegBit(MS_U32 u32Addr, MS_BOOL bEnable, MS_U8 u8Mask)
387 {
388 if (_hal_DMD.bBaseAddrInitialized)
389 {
390 RIU_WriteRegBit(u32Addr, bEnable, u8Mask);
391 }
392 else
393 {
394 #ifdef MS_DEBUG
395 printf("%s base address un-initialized\n", __FUNCTION__);
396 #endif
397 }
398 }
399
HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr,MS_U8 u8Value,MS_U8 u8Mask)400 void HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr, MS_U8 u8Value, MS_U8 u8Mask)
401 {
402 if (_hal_DMD.bBaseAddrInitialized)
403 {
404 RIU_WriteByteMask(u32Addr, u8Value, u8Mask);
405 }
406 else
407 {
408 #ifdef MS_DEBUG
409 printf("%s base address un-initialized\n", __FUNCTION__);
410 #endif
411 }
412 }
413
HAL_DMD_RIU_Write2Byte(MS_U32 u32Addr,MS_U16 u16Value)414 void HAL_DMD_RIU_Write2Byte(MS_U32 u32Addr, MS_U16 u16Value)
415 {
416 if (_hal_DMD.bBaseAddrInitialized)
417 {
418 RIU_Write2Byte(u32Addr, u16Value);
419 }
420 else
421 {
422 #ifdef MS_DEBUG
423 printf("%s base address un-initialized\n", __FUNCTION__);
424 #endif
425 }
426 }
427
428 //waiting add
HAL_DMD_IFAGC_RegRead(MS_U8 * ifagc_reg,MS_U8 * ifagc_reg_lsb,MS_U16 * ifagc_err)429 MS_BOOL HAL_DMD_IFAGC_RegRead(MS_U8 *ifagc_reg, MS_U8 *ifagc_reg_lsb, MS_U16 *ifagc_err)
430 {
431 MS_U8 status = true;
432 MS_U8 reg_tmp = 0, reg_tmp2 =0, reg_frz = 0;
433 // bank 5 0x24 [15:0] reg_agc_gain2_out
434 // use only high byte value
435
436 // select IF gain to read
437 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x22, 0x03);
438 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x04, ®_frz);
439 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x04, reg_frz | 0x80);
440 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x25, ®_tmp);
441 *ifagc_reg = reg_tmp;
442 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x24, ®_tmp);
443 *ifagc_reg_lsb = reg_tmp;
444 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x04, reg_frz);
445
446 #ifdef MS_DEBUG
447 printf("SSI_IFAGC_H = 0x%x 0x%x\n", *ifagc_reg,*ifagc_reg_lsb);
448 #endif
449
450 *ifagc_err = 0;
451 if(*ifagc_reg == 0xff)
452 {
453 // bank 5 0x04 [15] reg_tdp_lat
454 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x22, 0x00);
455 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x04, ®_frz);
456 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x04, reg_frz | 0x80);
457
458 // bank 5 0x2c [9:0] reg_agc_error
459 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x25, ®_tmp);
460 // if_agc_err = reg_tmp & 0x03;
461 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x24, ®_tmp2);
462 // if_agc_err = (if_agc_err << 6)|(reg_tmp >> 2);
463
464 if(reg_tmp&0x2)
465 {
466 *ifagc_err = ((((~reg_tmp)&0x03)<<8)|((~reg_tmp2)&0xff)) + 1;
467 }
468 else
469 {
470 *ifagc_err = reg_tmp<<8|reg_tmp2;
471 }
472
473 // release latch
474 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x04, reg_frz);
475 }
476
477
478 return status;
479 }
480
481 //waiting mark
482 #if(0)
HAL_DMD_GetRFLevel(float * fRFPowerDbmResult,float fRFPowerDbm,MS_U8 u8SarValue,DMD_RFAGC_SSI * pRfagcSsi,MS_U16 u16RfagcSsi_Size,DMD_IFAGC_SSI * pIfagcSsi_HiRef,MS_U16 u16IfagcSsi_HiRef_Size,DMD_IFAGC_SSI * pIfagcSsi_LoRef,MS_U16 u16IfagcSsi_LoRef_Size,DMD_IFAGC_ERR * pIfagcErr_LoRef,MS_U16 u16IfagcErr_LoRef_Size,DMD_IFAGC_ERR * pIfagcErr_HiRef,MS_U16 u16IfagcErr_HiRef_Size)483 MS_BOOL HAL_DMD_GetRFLevel(float *fRFPowerDbmResult, float fRFPowerDbm, MS_U8 u8SarValue,
484 DMD_RFAGC_SSI *pRfagcSsi, MS_U16 u16RfagcSsi_Size,
485 DMD_IFAGC_SSI *pIfagcSsi_HiRef, MS_U16 u16IfagcSsi_HiRef_Size,
486 DMD_IFAGC_SSI *pIfagcSsi_LoRef, MS_U16 u16IfagcSsi_LoRef_Size,
487 DMD_IFAGC_ERR *pIfagcErr_LoRef, MS_U16 u16IfagcErr_LoRef_Size,
488 DMD_IFAGC_ERR *pIfagcErr_HiRef, MS_U16 u16IfagcErr_HiRef_Size)
489 {
490 DMD_IFAGC_SSI *ifagc_ssi;
491 DMD_IFAGC_ERR *ifagc_err;
492 float ch_power_db=0.0f;
493 float ch_power_rf=0.0f;
494 float ch_power_if=0.0f, ch_power_ifa = 0.0f, ch_power_ifb =0.0f;
495 float ch_power_takeover=0.0f;
496 MS_U16 if_agc_err = 0;
497 MS_U8 status = true;
498 MS_U8 reg_tmp = 0, reg_tmp2 =0, reg_frz = 0,rf_agc_val =0,if_agc_val =0, if_agc_vala =0, if_agc_valb =0, if_agc_val_lsb =0, i;
499 MS_U8 ssi_tbl_len = 0, err_tbl_len = 0;
500
501 if ((pIfagcSsi_HiRef != NULL) && (pIfagcSsi_LoRef !=NULL))
502 {
503 // get RFAGC level
504 if (fRFPowerDbm>=100.0) // unreasonable input value, get RF level from RFAGG
505 {
506 rf_agc_val = u8SarValue;
507
508 ch_power_rf=pRfagcSsi[u16RfagcSsi_Size-1].power_db;
509 if (rf_agc_val >=pRfagcSsi[0].sar3_val)
510 {
511 float ch_power_rfa = 0, ch_power_rfb =0;
512 MS_U8 rf_agc_vala =0, rf_agc_valb =0;
513 for(i = 1; i < u16RfagcSsi_Size; i++)
514 {
515 if (rf_agc_val < pRfagcSsi[i].sar3_val)
516 {
517 rf_agc_valb = pRfagcSsi[i].sar3_val;
518 ch_power_rfb = pRfagcSsi[i].power_db;
519
520 i--;
521 rf_agc_vala = pRfagcSsi[i].sar3_val;
522 ch_power_rfa=pRfagcSsi[i].power_db;
523 while ((i>1) && (rf_agc_vala==pRfagcSsi[i-1].sar3_val))
524 {
525 ch_power_rfa=pRfagcSsi[i-1].power_db;
526 i--;
527 }
528 ch_power_rf = ch_power_rfa+(ch_power_rfb-ch_power_rfa)*(float)(rf_agc_val-rf_agc_vala)/(rf_agc_valb-rf_agc_vala);
529 break;
530 }
531 }
532 #ifdef MS_DEBUG
533 printf("RF Level from SAR:%f\n", ch_power_rf);
534 printf("SSI_RFAGC (SAR-4) = 0x%x\n", rf_agc_val);
535 printf("rf prev %f %x\n", ch_power_rfa, rf_agc_vala);
536 printf("rf next %f %x\n", ch_power_rfb, rf_agc_valb);
537 #endif
538 }
539 }
540 else
541 {
542 #ifdef MS_DEBUG
543 printf("RF Level from tuner: %f\n",fRFPowerDbm);
544 #endif
545 ch_power_rf = fRFPowerDbm;
546 }
547
548 // get IFAGC status
549 {
550 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x13, ®_tmp);
551
552 #ifdef MS_DEBUG
553 printf("AGC_REF = %d\n", (MS_U16)reg_tmp);
554 #endif
555
556 if (reg_tmp > 200)
557 {
558 ifagc_ssi = pIfagcSsi_HiRef;
559 ssi_tbl_len = u16IfagcSsi_HiRef_Size;
560 ifagc_err = pIfagcErr_HiRef;
561 err_tbl_len = u16IfagcErr_HiRef_Size;
562 }
563 else
564 {
565 ifagc_ssi = pIfagcSsi_LoRef;
566 ssi_tbl_len = u16IfagcSsi_LoRef_Size;
567 ifagc_err = pIfagcErr_LoRef;
568 err_tbl_len = u16IfagcErr_LoRef_Size;
569 }
570
571 // bank 5 0x24 [15:0] reg_agc_gain2_out
572 // use only high byte value
573
574 // select IF gain to read
575 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x03);
576 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, ®_frz);
577 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80);
578 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, ®_tmp);
579 if_agc_val = reg_tmp;
580 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x18, ®_tmp);
581 if_agc_val_lsb = reg_tmp;
582 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz);
583 #ifdef MS_DEBUG
584 printf("SSI_IFAGC_H = 0x%x 0x%x\n", if_agc_val,if_agc_val_lsb);
585 #endif
586
587 ch_power_if=ifagc_ssi[0].power_db;
588 if (if_agc_val >=ifagc_ssi[0].agc_val)
589 {
590 for(i = 1; i < ssi_tbl_len; i++)
591 {
592 if (if_agc_val < ifagc_ssi[i].agc_val)
593 {
594 if_agc_valb = ifagc_ssi[i].agc_val;
595 ch_power_ifb = ifagc_ssi[i].power_db;
596
597 i--;
598 if_agc_vala = ifagc_ssi[i].agc_val;
599 ch_power_ifa=ifagc_ssi[i].power_db;
600 while ((i>1) && (if_agc_vala==ifagc_ssi[i-1].agc_val))
601 {
602 ch_power_ifa=ifagc_ssi[i-1].power_db;
603 i--;
604 }
605 ch_power_if = ch_power_ifa+(ch_power_ifb-ch_power_ifa)*(float)((if_agc_val-if_agc_vala)*256+if_agc_val_lsb)/((if_agc_valb-if_agc_vala)*256);
606 break;
607 }
608 }
609 }
610 #ifdef MS_DEBUG
611 printf("if prev %f %x\n", ch_power_ifa, if_agc_vala);
612 printf("if next %f %x\n", ch_power_ifb, if_agc_valb);
613 #endif
614
615 for(i = 0; i < ssi_tbl_len; i++)
616 {
617 if (ifagc_ssi[i].agc_val <= ifagc_ssi[i+1].agc_val)
618 {
619 ch_power_takeover = ifagc_ssi[i+1].power_db;
620 break;
621 }
622 }
623
624 #ifdef MS_DEBUG
625 printf("ch_power_rf = %f\n", ch_power_rf);
626 printf("ch_power_if = %f\n", ch_power_if);
627 printf("ch_power_takeover = %f\n", ch_power_takeover);
628 #endif
629
630 // ch_power_db = (ch_power_rf > ch_power_if)? ch_power_rf : ch_power_if;
631
632 if(ch_power_rf > (ch_power_takeover + 0.5))
633 {
634 ch_power_db = ch_power_rf;
635 }
636 else if(ch_power_if < (ch_power_takeover - 0.5))
637 {
638 ch_power_db = ch_power_if;
639 }
640 else
641 {
642 ch_power_db = (ch_power_if + ch_power_rf)/2;
643 }
644
645 // ch_power_db = (ch_power_rf > ch_power_if)? ch_power_if : ch_power_rf;
646
647 ///////// IF-AGC Error for Add. Attnuation /////////////
648 if(if_agc_val == 0xff)
649 {
650 #if 0
651 #if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD )
652 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x22, ®_tmp);
653 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x22, (reg_tmp&0xf0));
654 #endif
655 #endif
656 // bank 5 0x04 [15] reg_tdp_lat
657 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x16, 0x00);
658 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x03, ®_frz);
659 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz | 0x80);
660 #if 0
661 //#if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD )
662 // bank 5 0x2c [9:0] reg_agc_error
663 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x25, ®_tmp);
664 // if_agc_err = reg_tmp & 0x03;
665 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x24, ®_tmp2);
666 // if_agc_err = (if_agc_err << 6)|(reg_tmp >> 2);
667 //#else
668 #endif
669 // bank 5 0x2c [9:0] reg_agc_error
670 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x19, ®_tmp);
671 // if_agc_err = reg_tmp & 0x03;
672 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDF_REG_BASE + 0x18, ®_tmp2);
673 // if_agc_err = (if_agc_err << 6)|(reg_tmp >> 2);
674 //#endif
675
676 if(reg_tmp&0x2)
677 {
678 if_agc_err = ((((~reg_tmp)&0x03)<<8)|((~reg_tmp2)&0xff)) + 1;
679 }
680 else
681 {
682 if_agc_err = reg_tmp<<8|reg_tmp2;
683 }
684
685 // release latch
686 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDF_REG_BASE + 0x03, reg_frz);
687
688 for(i = 0; i < err_tbl_len; i++)
689 {
690 if ( if_agc_err <= ifagc_err[i].agc_err ) // signed char comparison
691 {
692 ch_power_db += ifagc_err[i].attn_db;
693 break;
694 }
695 }
696 #ifdef MS_DEBUG
697 printf("if_agc_err = 0x%x\n", if_agc_err);
698 #endif
699 }
700
701 // BY 20110812 temporaily remove ch_power_db += SIGNAL_LEVEL_OFFSET;
702 }
703 }
704 else
705 {
706 #ifdef MS_DEBUG
707 if (fRFPowerDbm>=100.0) // unreasonable input value, get RF level from RFAGG
708 {
709 printf("Error!! please add AGC table\n");
710 }
711 #endif
712 ch_power_db = fRFPowerDbm;
713 }
714 *fRFPowerDbmResult=ch_power_db;
715 return status;
716 }
717 #endif
718
719 //bryan temp mark
720 #if(0)
HAL_DMD_GetNordigSSI(float fPrel,MS_U16 * strength)721 void HAL_DMD_GetNordigSSI(float fPrel, MS_U16 *strength)
722 {
723 if (fPrel<-15.0f)
724 {
725 *strength = 0;
726 }
727 else if (fPrel<0.0f)
728 {
729 *strength = (MS_U16)((2.0f/3.0f)*(fPrel+15.0f));
730 }
731 else if (fPrel<20.0f)
732 {
733 *strength = (MS_U16)(4.0f*fPrel+10.0f);
734 }
735 else if (fPrel<35.0f)
736 {
737 *strength = (MS_U16)((2.0f/3.0f)*(fPrel-20.0f)+90.0f);
738 }
739 else
740 {
741 *strength = 100;
742 }
743
744 }
745 #endif
746 /*
747 from Steven.Hung
748 2. �n��T12 TS1 TS bus tristate
749 Set Bank CHIPTOP, 0x57[13:11]=3��h0; (reg_ts1config[2:0]=0)
750 3. �n��T12 IFAGC tristate
751 Set Bank CHIPTOP, 0x2[12]=1��h1; (reg_if_agc_pad_oen=1)
752 */
HAL_DMD_TS1_Tristate(MS_BOOL bEnable)753 void HAL_DMD_TS1_Tristate(MS_BOOL bEnable)
754 {
755 #ifdef MS_DEBUG
756 printf("HAL_DMD_TS1_Tristate %d\n",bEnable);
757 #endif
758 if (bEnable)
759 {
760 HAL_DMD_RIU_WriteByteMask(0x101EAF, 0, BMASK(5:3));
761 }
762 else
763 {
764 HAL_DMD_RIU_WriteByteMask(0x101EAF, (BIT_(5))|(BIT_(4))|(BIT_(3)), BMASK(5:3));
765 }
766 }
767
HAL_DMD_RFAGC_Tristate(MS_BOOL bEnable)768 void HAL_DMD_RFAGC_Tristate(MS_BOOL bEnable)
769 {
770 MS_U8 u8RegMuxBackup = 0;
771
772 #ifdef MS_DEBUG
773 printf("HAL_DMD_RFAGC_Tristate %d\n",bEnable);
774 #endif
775 u8RegMuxBackup = HAL_DMD_RIU_ReadByte(0x101E39);
776 HAL_DMD_RIU_WriteByte(0x101E39, 0x00); //mux from DMD MCU to HK
777 if (bEnable)
778 {
779 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(0)));
780
781 }
782 else
783 {
784 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(0)), (BIT_(0)));
785 }
786 HAL_DMD_RIU_WriteByte(0x101E39, u8RegMuxBackup); //mux from HK to DMD MCU
787 }
788
HAL_DMD_IFAGC_Tristate(MS_BOOL bEnable)789 void HAL_DMD_IFAGC_Tristate(MS_BOOL bEnable)
790 {
791 MS_U8 u8RegMuxBackup = 0;
792
793 #ifdef MS_DEBUG
794 printf("HAL_DMD_IFAGC_Tristate %d\n",bEnable);
795 #endif
796 u8RegMuxBackup = HAL_DMD_RIU_ReadByte(0x101E39);
797 HAL_DMD_RIU_WriteByte(0x101E39, 0x00); //mux from DMD MCU to HK
798 if (bEnable)
799 {
800 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(4)));
801 }
802 else
803 {
804 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(4)), (BIT_(4)));
805 }
806 HAL_DMD_RIU_WriteByte(0x101E39, u8RegMuxBackup); //mux from HK to DMD MCU
807 }
808
HAL_DMD_IFAGC_TS_Tristate(MS_BOOL bEnable)809 void HAL_DMD_IFAGC_TS_Tristate(MS_BOOL bEnable)
810 {
811 #ifdef MS_DEBUG
812 printf("HAL_DMD_IFAGC_TS_Tristate %d\n",bEnable);
813 #endif
814 HAL_DMD_TS1_Tristate(bEnable);
815 HAL_DMD_IFAGC_Tristate(bEnable);
816 }
817
818 #if(0)
HAL_DMD_TS_GetClockRate(float * fTS_CLK)819 MS_BOOL HAL_DMD_TS_GetClockRate(float *fTS_CLK)
820 {
821 // from Raymond
822 *fTS_CLK=(HAL_DMD_RIU_ReadRegBit(0x103301, BIT_(0)) ? 288.0 : 348.0)/(2*((HAL_DMD_RIU_ReadByte(0x103300)&BMASK(4:0))+1));
823 return TRUE;
824 }
825 #endif
HAL_DMD_ADC_IMUX_Sel(MS_U8 u8PadSel,MS_BOOL bPGAEnable)826 static void HAL_DMD_ADC_IMUX_Sel(MS_U8 u8PadSel, MS_BOOL bPGAEnable)
827 {
828 if (u8PadSel==0)
829 {
830 HAL_DMD_RIU_WriteByteMask(0x112802, 4<<4, BMASK(6:4));
831 }
832 else
833 {
834 if (bPGAEnable)
835 {
836 HAL_DMD_RIU_WriteByteMask(0x112802, 1<<4, BMASK(6:4));
837 }
838 else
839 {
840 HAL_DMD_RIU_WriteByteMask(0x112802, 2<<4, BMASK(6:4));
841 }
842 }
843 }
844
HAL_DMD_ADC_QMUX_Sel(MS_U8 u8PadSel,MS_BOOL bPGAEnable)845 static void HAL_DMD_ADC_QMUX_Sel(MS_U8 u8PadSel, MS_BOOL bPGAEnable)
846 {
847 if (u8PadSel==0)
848 {
849 HAL_DMD_RIU_WriteByteMask(0x112803, 4, BMASK(2:0));
850 }
851 else
852 {
853 if (bPGAEnable)
854 {
855 HAL_DMD_RIU_WriteByteMask(0x112803, 1, BMASK(2:0));
856 }
857 else
858 {
859 HAL_DMD_RIU_WriteByteMask(0x112803, 2, BMASK(2:0));
860 }
861 }
862 }
863
864
HAL_DMD_SIF_PGA_Ctl(MS_BOOL bPGAEnable)865 static void HAL_DMD_SIF_PGA_Ctl(MS_BOOL bPGAEnable)
866 {
867 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA
868 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping
869 }
870
HAL_DMD_VIF_PGA_Ctl(MS_BOOL bPGAEnable)871 static void HAL_DMD_VIF_PGA_Ctl(MS_BOOL bPGAEnable)
872 {
873 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA
874 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping
875 }
876
877 /************************************************************************************************
878 Subject: ADC I/Q Switch (After Init CLKGen)
879 Function: HAL_DMD_ADC_IQ_Switch
880 Parmeter: u8ADCIQMode : 0=I path, 1=Q path, 2=both IQ
881 Parmeter: u8PadSel : 0=Normal, 1=analog pad
882 Parmeter: bPGAEnable : 0=disable, 1=enable
883 Parmeter: u8PGAGain : default 5
884 Return: MS_BOOL :
885 Remark:
886 *************************************************************************************************/
HAL_DMD_ADC_IQ_Switch(MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain)887 MS_BOOL HAL_DMD_ADC_IQ_Switch(MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain)
888 {
889 MS_U8 u8RegMuxBackup = 0;
890 u8PGAGain=u8PGAGain;
891 #ifdef MS_DEBUG
892 printf("HAL_DMD_ADC_IQ_Switch %d %d %d %d\n",u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
893 #endif
894
895 u8RegMuxBackup = HAL_DMD_RIU_ReadByte(0x101E39);
896 HAL_DMD_RIU_WriteByte(0x101E39, 0x00); //mux from DMD MCU to HK
897 #ifdef MS_DEBUG
898 printf("before 0x112803 %x\n",HAL_DMD_RIU_ReadByte(0x112803));
899 #endif
900 switch(u8ADCIQMode)
901 {
902 case 0://Normal case, I path
903 default:
904 HAL_DMD_RIU_WriteRegBit(0x112818, 0, BIT_(0)); // power on I ADC
905 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(1)); // power down Q ADC
906 HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(4)); // ADC clock out swap 0:no swap, 1:swap
907 HAL_DMD_RIU_WriteRegBit(0x112803, 0, BIT_(5)); // ADC clock out select 0:I, 1:Q
908 HAL_DMD_ADC_IMUX_Sel(u8PadSel, bPGAEnable);
909 HAL_DMD_SIF_PGA_Ctl(bPGAEnable);
910 HAL_DMD_VIF_PGA_Ctl(FALSE);
911 break;
912 case 1://VIF, Q path, for internal signal saw
913 HAL_DMD_RIU_WriteRegBit(0x112818, 1, BIT_(0)); // power down I ADC
914 HAL_DMD_RIU_WriteRegBit(0x112818, 0, BIT_(1)); // power on Q ADC
915 HAL_DMD_RIU_WriteRegBit(0x112803, 1, BIT_(4)); // ADC clock out swap 0:no swap, 1:swap
916 HAL_DMD_RIU_WriteRegBit(0x112803, 1, BIT_(5)); // ADC clock out select 0:I, 1:Q
917 HAL_DMD_ADC_QMUX_Sel(u8PadSel, bPGAEnable);
918 HAL_DMD_SIF_PGA_Ctl(FALSE);
919 HAL_DMD_VIF_PGA_Ctl(bPGAEnable);
920 break;
921 case 2://both IQ, for ZIF tuner
922 break;
923 }
924 #ifdef MS_DEBUG
925 printf("after 0x112803 %x\n",HAL_DMD_RIU_ReadByte(0x112803));
926 #endif
927 HAL_DMD_RIU_WriteByte(0x101E39, u8RegMuxBackup); //mux from HK to DMD MCU
928 return TRUE;
929 }
930
931 /************************************************************************************************
932 Subject: HAL_DMD_TSO_Clk_Control
933 Function: ts output clock frequency and phase configure
934 Parmeter: u8cmd_array, clock div, 0x01, div (0x00~0x1f),
935 clock phase inv, 0x02, inv_en (0,1),
936 clock phase tuning, 0x03, phase_tuning_en (0,1), tuning_num (0x00~0x1f)
937 Return: MS_BOOL
938 Remark:
939 *************************************************************************************************/
HAL_DMD_TSO_Clk_Control(MS_U8 * u8cmd_array)940 MS_BOOL HAL_DMD_TSO_Clk_Control(MS_U8 *u8cmd_array)
941 {
942 MS_U8 u8Temp;
943
944 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
945
946 if ( (u8Temp&0x01) == 0x00)
947 {
948 printf("[utopia][halDMD]Error!!!, we shall select clk_dmplldiv3\n");
949 return false;
950 }
951 switch (u8cmd_array[0])
952 {
953 case 0x01: // clock frequency,div
954 {
955 MS_U8 u8data = 0;
956 u8data = HAL_DMD_RIU_ReadByte(0x103300);
957 u8data &= (0xff-0x1f);
958 u8data |= (u8cmd_array[1]&0x1f);
959 HAL_DMD_RIU_WriteByte(0x103300, u8data);
960 }
961 break;
962 case 0x02: // clock phase inv or not.
963 {
964 MS_U8 u8data = 0;
965 u8data = HAL_DMD_RIU_ReadByte(0x103301);
966 u8data &= (0xff-0x02);
967 u8data |= ((u8cmd_array[1]&0x01)<<1);
968 HAL_DMD_RIU_WriteByte(0x103301, u8data);
969 }
970 break;
971 case 0x03:
972 {
973 MS_U8 u8data = 0;
974
975 u8data = HAL_DMD_RIU_ReadByte(0x103301);
976 u8data &= (0xff-0x10);
977 u8data |= ((u8cmd_array[1]&0x01)<<4);
978 HAL_DMD_RIU_WriteByte(0x103301, u8data);
979
980 u8data = HAL_DMD_RIU_ReadByte(0x103300+(0x05<<1)+1);
981 u8data &= (0xff-0x1f);
982 u8data |= (u8cmd_array[2]&0x1f);
983 HAL_DMD_RIU_WriteByte(0x103300+(0x05<<1)+1, u8data);
984 }
985 break;
986 default:
987 printf("[utopia][halDMD]Error!!!, cmd invalid\n");
988 break;
989
990 }
991 #ifdef MS_DEBUG
992 printf("0x103300: 0x%x\n",HAL_DMD_RIU_ReadByte(0x103300));
993 printf("0x103301: 0x%x\n",HAL_DMD_RIU_ReadByte(0x103301));
994 printf("0x10330B: 0x%x\n",HAL_DMD_RIU_ReadByte(0x10330B));
995 #endif
996 return true;
997 }
998
999 /****************************************************************************
1000 Subject: Function providing approx. result of Log10(X)
1001 Function: Log10Approx
1002 Parmeter: Operand X in float
1003 Return: Approx. value of Log10(X) in float
1004 Remark: Ouput range from 0.0, 0.3 to 9.6 (input 1 to 2^32)
1005 *****************************************************************************/
1006 //bryan temp mark
1007 #if(0)
1008
1009
1010 #if 1
1011 const float _LogApproxTableX[80] =
1012 { 1.00, 1.30, 1.69, 2.20, 2.86, 3.71, 4.83, 6.27, 8.16, 10.60, 13.79,
1013 17.92, 23.30, 30.29, 39.37, 51.19, 66.54, 86.50, 112.46, 146.19,
1014 190.05, 247.06, 321.18, 417.54, 542.80, 705.64, 917.33, 1192.53,
1015 1550.29, 2015.38, 2620.00, 3405.99, 4427.79, 5756.13, 7482.97,
1016 9727.86, 12646.22, 16440.08, 21372.11, 27783.74, 36118.86,
1017 46954.52, 61040.88, 79353.15, 103159.09, 134106.82, 174338.86,
1018 226640.52, 294632.68, 383022.48, 497929.22, 647307.99, 841500.39, 1093950.50,
1019 1422135.65, 1848776.35, 2403409.25, 3124432.03, 4061761.64, 5280290.13,
1020 6864377.17, 8923690.32, 11600797.42, 15081036.65, 19605347.64, 25486951.94,
1021 33133037.52, 43072948.77, 55994833.40, 72793283.42, 94631268.45,
1022 123020648.99, 159926843.68, 207904896.79, 270276365.82, 351359275.57,
1023 456767058.24, 593797175.72, 771936328.43, 1003517226.96
1024 };
1025
1026 const float _LogApproxTableY[80] =
1027 { 0.00, 0.11, 0.23, 0.34, 0.46, 0.57, 0.68, 0.80, 0.91, 1.03, 1.14, 1.25,
1028 1.37, 1.48, 1.60, 1.71, 1.82, 1.94, 2.05, 2.16, 2.28, 2.39, 2.51, 2.62,
1029 2.73, 2.85, 2.96, 3.08, 3.19, 3.30, 3.42, 3.53, 3.65, 3.76, 3.87, 3.99,
1030 4.10, 4.22, 4.33, 4.44, 4.56, 4.67, 4.79, 4.90, 5.01, 5.13, 5.24, 5.36,
1031 5.47, 5.58, 5.70, 5.81, 5.93, 6.04, 6.15, 6.27, 6.04, 6.15, 6.27, 6.38,
1032 6.49, 6.61, 6.72, 6.84, 6.95, 7.06, 7.18, 7.29, 7.41, 7.52, 7.63, 7.75,
1033 7.86, 7.98, 8.09, 8.20, 8.32, 8.43, 8.55, 8.66
1034 };
1035
Log10Approx(float flt_x)1036 float Log10Approx(float flt_x)
1037 {
1038 MS_U8 indx = 0;
1039
1040 do {
1041 if (flt_x < _LogApproxTableX[indx])
1042 break;
1043 indx++;
1044 }while (indx < 79); //stop at indx = 80
1045
1046 return _LogApproxTableY[indx];
1047 }
1048 #else
Log10Approx(float flt_x)1049 float Log10Approx(float flt_x)
1050 {
1051 MS_U32 u32_temp = 1;
1052 MS_U8 indx = 0;
1053
1054 do {
1055 u32_temp = u32_temp << 1;
1056 if (flt_x < (float)u32_temp)
1057 break;
1058 }while (++indx < 32);
1059
1060 // 10*log10(X) ~= 0.3*N, when X ~= 2^N
1061 return (float)0.3 * indx;
1062 }
1063 #endif
1064 #endif
1065