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Searched refs:T2SNR_REG_BASE (Results 1 – 24 of 24) sorted by relevance

/utopia/UTPA2-700.0.x/modules/demodulator/hal/maldives/demod/
H A DhalDMD_INTERN_DVBT2.c424 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
425 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2SNR_REG_BASE+(0x23*2)+1, (u8Data|0x01)); in INTERN_DVBT2_SoftReset()
443 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
H A DhalDMD_INTERN_common.h113 #define T2SNR_REG_BASE 0x2c00 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/manhattan/demod/
H A DhalDMD_INTERN_DVBT2.c435 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
436 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2SNR_REG_BASE+(0x23*2)+1, (u8Data|0x01)); in INTERN_DVBT2_SoftReset()
454 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
H A DhalDMD_INTERN_common.h116 #define T2SNR_REG_BASE 0x2c00 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/macan/demod/
H A DhalDMD_INTERN_DVBT2.c444 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
445 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2SNR_REG_BASE+(0x23*2)+1, (u8Data|0x01)); in INTERN_DVBT2_SoftReset()
463 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
H A DhalDMD_INTERN_common.h117 #define T2SNR_REG_BASE 0x2c00 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mustang/demod/
H A DhalDMD_INTERN_DVBT2.c449 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
450 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2SNR_REG_BASE+(0x23*2)+1, (u8Data|0x01)); in INTERN_DVBT2_SoftReset()
468 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
H A DhalDMD_INTERN_common.h114 #define T2SNR_REG_BASE 0x2c00 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/kano/demod/
H A DhalDMD_INTERN_common.h116 #define T2SNR_REG_BASE 0x2c00 macro
H A DhalDMD_INTERN_DVBT2.c441 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
442 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2SNR_REG_BASE+(0x23*2)+1, (u8Data|0x01)); in INTERN_DVBT2_SoftReset()
460 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maserati/demod/
H A DhalDMD_INTERN_common.h116 #define T2SNR_REG_BASE 0x2c00 macro
H A DhalDMD_INTERN_DVBT2.c441 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
442 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2SNR_REG_BASE+(0x23*2)+1, (u8Data|0x01)); in INTERN_DVBT2_SoftReset()
460 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maxim/demod/
H A DhalDMD_INTERN_common.h117 #define T2SNR_REG_BASE 0x2c00 macro
H A DhalDMD_INTERN_DVBT2.c454 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
455 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2SNR_REG_BASE+(0x23*2)+1, (u8Data|0x01)); in INTERN_DVBT2_SoftReset()
473 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7821/demod/
H A DhalDMD_INTERN_common.h116 #define T2SNR_REG_BASE 0x2c00 macro
H A DhalDMD_INTERN_DVBT2.c441 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
442 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2SNR_REG_BASE+(0x23*2)+1, (u8Data|0x01)); in INTERN_DVBT2_SoftReset()
460 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6/demod/
H A DhalDMD_INTERN_common.h116 #define T2SNR_REG_BASE 0x2c00 macro
H A DhalDMD_INTERN_DVBT2.c441 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
442 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2SNR_REG_BASE+(0x23*2)+1, (u8Data|0x01)); in INTERN_DVBT2_SoftReset()
460 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/curry/demod/
H A DhalDMD_INTERN_common.h116 #define T2SNR_REG_BASE 0x2c00 macro
H A DhalDMD_INTERN_DVBT2.c441 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
442 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2SNR_REG_BASE+(0x23*2)+1, (u8Data|0x01)); in INTERN_DVBT2_SoftReset()
460 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6lite/demod/
H A DhalDMD_INTERN_common.h117 #define T2SNR_REG_BASE 0x2c00 macro
H A DhalDMD_INTERN_DVBT2.c441 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
442 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2SNR_REG_BASE+(0x23*2)+1, (u8Data|0x01)); in INTERN_DVBT2_SoftReset()
460 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7621/demod/
H A DhalDMD_INTERN_common.h117 #define T2SNR_REG_BASE 0x2c00 macro
H A DhalDMD_INTERN_DVBT2.c454 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
455 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2SNR_REG_BASE+(0x23*2)+1, (u8Data|0x01)); in INTERN_DVBT2_SoftReset()
473 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()