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Searched refs:T2FEC_REG_BASE (Results 1 – 24 of 24) sorted by relevance

/utopia/UTPA2-700.0.x/modules/demodulator/hal/maserati/demod/
H A DhalDMD_INTERN_DVBT2.c1689 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction in INTERN_DVBT2_GetPostLdpcBer()
1692 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1694 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1699 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1701 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1703 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1705 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 0, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1709 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00); // avoid confliction in INTERN_DVBT2_GetPostLdpcBer()
1738 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction
1741 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg);
[all …]
H A DhalDMD_INTERN_common.h113 #define T2FEC_REG_BASE 0x3300 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/kano/demod/
H A DhalDMD_INTERN_DVBT2.c1689 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction in INTERN_DVBT2_GetPostLdpcBer()
1692 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1694 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1699 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1701 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1703 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1705 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 0, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1709 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00); // avoid confliction in INTERN_DVBT2_GetPostLdpcBer()
1738 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction
1741 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg);
[all …]
H A DhalDMD_INTERN_common.h113 #define T2FEC_REG_BASE 0x3300 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7621/demod/
H A DhalDMD_INTERN_DVBT2.c1737 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction in INTERN_DVBT2_GetPostLdpcBer()
1740 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1742 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1747 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1749 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1751 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1753 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 0, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1757 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00); // avoid confliction in INTERN_DVBT2_GetPostLdpcBer()
1786 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction
1789 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg);
[all …]
H A DhalDMD_INTERN_common.h114 #define T2FEC_REG_BASE 0x3300 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6/demod/
H A DhalDMD_INTERN_DVBT2.c1689 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction in INTERN_DVBT2_GetPostLdpcBer()
1692 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1694 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1699 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1701 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1703 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1705 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 0, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1709 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00); // avoid confliction in INTERN_DVBT2_GetPostLdpcBer()
1738 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction
1741 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg);
[all …]
H A DhalDMD_INTERN_common.h113 #define T2FEC_REG_BASE 0x3300 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/curry/demod/
H A DhalDMD_INTERN_DVBT2.c1689 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction in INTERN_DVBT2_GetPostLdpcBer()
1692 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1694 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1699 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1701 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1703 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1705 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 0, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1709 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00); // avoid confliction in INTERN_DVBT2_GetPostLdpcBer()
1738 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction
1741 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg);
[all …]
H A DhalDMD_INTERN_common.h113 #define T2FEC_REG_BASE 0x3300 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6lite/demod/
H A DhalDMD_INTERN_DVBT2.c1689 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction in INTERN_DVBT2_GetPostLdpcBer()
1692 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1694 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1699 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1701 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1703 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1705 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 0, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1709 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00); // avoid confliction in INTERN_DVBT2_GetPostLdpcBer()
1738 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction
1741 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg);
[all …]
H A DhalDMD_INTERN_common.h114 #define T2FEC_REG_BASE 0x3300 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7821/demod/
H A DhalDMD_INTERN_DVBT2.c1689 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction in INTERN_DVBT2_GetPostLdpcBer()
1692 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1694 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1699 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1701 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1703 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1705 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 0, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1709 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00); // avoid confliction in INTERN_DVBT2_GetPostLdpcBer()
1738 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction
1741 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg);
[all …]
H A DhalDMD_INTERN_common.h113 #define T2FEC_REG_BASE 0x3300 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maxim/demod/
H A DhalDMD_INTERN_DVBT2.c1737 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction in INTERN_DVBT2_GetPostLdpcBer()
1740 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1742 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1747 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1749 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1751 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1753 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 0, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1757 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00); // avoid confliction in INTERN_DVBT2_GetPostLdpcBer()
1786 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction
1789 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg);
[all …]
H A DhalDMD_INTERN_common.h114 #define T2FEC_REG_BASE 0x3300 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maldives/demod/
H A DhalDMD_INTERN_DVBT2.c1634 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction in INTERN_DVBT2_GetPostLdpcBer()
1637 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1639 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1644 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1646 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1648 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1650 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 0, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1654 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00); // avoid confliction in INTERN_DVBT2_GetPostLdpcBer()
1710 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction in INTERN_DVBT2_GetPreLdpcBer()
1713 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg); in INTERN_DVBT2_GetPreLdpcBer()
[all …]
H A DhalDMD_INTERN_common.h110 #define T2FEC_REG_BASE 0x3300 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/manhattan/demod/
H A DhalDMD_INTERN_DVBT2.c1693 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction in INTERN_DVBT2_GetPostLdpcBer()
1696 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1698 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1703 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1705 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1707 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1709 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 0, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1713 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00); // avoid confliction in INTERN_DVBT2_GetPostLdpcBer()
1769 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction in INTERN_DVBT2_GetPreLdpcBer()
1772 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg); in INTERN_DVBT2_GetPreLdpcBer()
[all …]
H A DhalDMD_INTERN_common.h113 #define T2FEC_REG_BASE 0x3300 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/macan/demod/
H A DhalDMD_INTERN_DVBT2.c1727 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction in INTERN_DVBT2_GetPostLdpcBer()
1730 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1732 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1737 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1739 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1741 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1743 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 0, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1747 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00); // avoid confliction in INTERN_DVBT2_GetPostLdpcBer()
1803 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction in INTERN_DVBT2_GetPreLdpcBer()
1806 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg); in INTERN_DVBT2_GetPreLdpcBer()
[all …]
H A DhalDMD_INTERN_common.h114 #define T2FEC_REG_BASE 0x3300 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mustang/demod/
H A DhalDMD_INTERN_DVBT2.c1734 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction in INTERN_DVBT2_GetPostLdpcBer()
1737 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1739 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1744 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1746 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1748 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1750 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 0, &reg); in INTERN_DVBT2_GetPostLdpcBer()
1754 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00); // avoid confliction in INTERN_DVBT2_GetPostLdpcBer()
1810 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction in INTERN_DVBT2_GetPreLdpcBer()
1813 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, &reg); in INTERN_DVBT2_GetPreLdpcBer()
[all …]
H A DhalDMD_INTERN_common.h111 #define T2FEC_REG_BASE 0x3300 macro