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Searched refs:T2FDP_REG_BASE (Results 1 – 24 of 24) sorted by relevance

/utopia/UTPA2-700.0.x/modules/demodulator/hal/maserati/demod/
H A DhalDMD_INTERN_DVBT2.c429 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x17*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
430 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+(0x17*2)+1, (u8Data|0x10)); in INTERN_DVBT2_SoftReset()
432 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+0xff, 0x10); in INTERN_DVBT2_SoftReset()
456 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x18*2), &u8Data); in INTERN_DVBT2_SoftReset()
2213 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+0x01*2, &reg); in INTERN_DVBT2_GetSNR()
2274 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+0x01*2, &reg);
H A DhalDMD_INTERN_common.h112 #define T2FDP_REG_BASE 0x3100 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/kano/demod/
H A DhalDMD_INTERN_DVBT2.c429 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x17*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
430 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+(0x17*2)+1, (u8Data|0x10)); in INTERN_DVBT2_SoftReset()
432 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+0xff, 0x10); in INTERN_DVBT2_SoftReset()
456 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x18*2), &u8Data); in INTERN_DVBT2_SoftReset()
2213 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+0x01*2, &reg); in INTERN_DVBT2_GetSNR()
2274 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+0x01*2, &reg);
H A DhalDMD_INTERN_common.h112 #define T2FDP_REG_BASE 0x3100 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7621/demod/
H A DhalDMD_INTERN_DVBT2.c442 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x17*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
443 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+(0x17*2)+1, (u8Data|0x10)); in INTERN_DVBT2_SoftReset()
445 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+0xff, 0x10); in INTERN_DVBT2_SoftReset()
469 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x18*2), &u8Data); in INTERN_DVBT2_SoftReset()
2261 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+0x01*2, &reg); in INTERN_DVBT2_GetSNR()
2322 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+0x01*2, &reg);
H A DhalDMD_INTERN_common.h113 #define T2FDP_REG_BASE 0x3100 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6/demod/
H A DhalDMD_INTERN_DVBT2.c429 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x17*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
430 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+(0x17*2)+1, (u8Data|0x10)); in INTERN_DVBT2_SoftReset()
432 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+0xff, 0x10); in INTERN_DVBT2_SoftReset()
456 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x18*2), &u8Data); in INTERN_DVBT2_SoftReset()
2213 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+0x01*2, &reg); in INTERN_DVBT2_GetSNR()
2274 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+0x01*2, &reg);
H A DhalDMD_INTERN_common.h112 #define T2FDP_REG_BASE 0x3100 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/curry/demod/
H A DhalDMD_INTERN_DVBT2.c429 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x17*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
430 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+(0x17*2)+1, (u8Data|0x10)); in INTERN_DVBT2_SoftReset()
432 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+0xff, 0x10); in INTERN_DVBT2_SoftReset()
456 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x18*2), &u8Data); in INTERN_DVBT2_SoftReset()
2213 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+0x01*2, &reg); in INTERN_DVBT2_GetSNR()
2274 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+0x01*2, &reg);
H A DhalDMD_INTERN_common.h112 #define T2FDP_REG_BASE 0x3100 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6lite/demod/
H A DhalDMD_INTERN_DVBT2.c429 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x17*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
430 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+(0x17*2)+1, (u8Data|0x10)); in INTERN_DVBT2_SoftReset()
432 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+0xff, 0x10); in INTERN_DVBT2_SoftReset()
456 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x18*2), &u8Data); in INTERN_DVBT2_SoftReset()
2213 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+0x01*2, &reg); in INTERN_DVBT2_GetSNR()
2274 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+0x01*2, &reg);
H A DhalDMD_INTERN_common.h113 #define T2FDP_REG_BASE 0x3100 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7821/demod/
H A DhalDMD_INTERN_DVBT2.c429 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x17*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
430 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+(0x17*2)+1, (u8Data|0x10)); in INTERN_DVBT2_SoftReset()
432 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+0xff, 0x10); in INTERN_DVBT2_SoftReset()
456 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x18*2), &u8Data); in INTERN_DVBT2_SoftReset()
2213 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+0x01*2, &reg); in INTERN_DVBT2_GetSNR()
2274 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+0x01*2, &reg);
H A DhalDMD_INTERN_common.h112 #define T2FDP_REG_BASE 0x3100 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maxim/demod/
H A DhalDMD_INTERN_DVBT2.c442 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x17*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
443 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+(0x17*2)+1, (u8Data|0x10)); in INTERN_DVBT2_SoftReset()
445 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+0xff, 0x10); in INTERN_DVBT2_SoftReset()
469 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x18*2), &u8Data); in INTERN_DVBT2_SoftReset()
2261 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+0x01*2, &reg); in INTERN_DVBT2_GetSNR()
2322 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+0x01*2, &reg);
H A DhalDMD_INTERN_common.h113 #define T2FDP_REG_BASE 0x3100 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maldives/demod/
H A DhalDMD_INTERN_DVBT2.c412 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x17*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
413 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+(0x17*2)+1, (u8Data|0x10)); in INTERN_DVBT2_SoftReset()
415 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+0xff, 0x10); in INTERN_DVBT2_SoftReset()
439 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x18*2), &u8Data); in INTERN_DVBT2_SoftReset()
1954 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+0x01*2, &reg); in INTERN_DVBT2_GetSNR()
H A DhalDMD_INTERN_common.h109 #define T2FDP_REG_BASE 0x3100 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/manhattan/demod/
H A DhalDMD_INTERN_DVBT2.c423 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x17*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
424 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+(0x17*2)+1, (u8Data|0x10)); in INTERN_DVBT2_SoftReset()
426 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+0xff, 0x10); in INTERN_DVBT2_SoftReset()
450 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x18*2), &u8Data); in INTERN_DVBT2_SoftReset()
2116 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+0x01*2, &reg); in INTERN_DVBT2_GetSNR()
H A DhalDMD_INTERN_common.h112 #define T2FDP_REG_BASE 0x3100 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/macan/demod/
H A DhalDMD_INTERN_DVBT2.c432 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x17*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
433 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+(0x17*2)+1, (u8Data|0x10)); in INTERN_DVBT2_SoftReset()
435 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+0xff, 0x10); in INTERN_DVBT2_SoftReset()
459 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x18*2), &u8Data); in INTERN_DVBT2_SoftReset()
2150 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+0x01*2, &reg); in INTERN_DVBT2_GetSNR()
H A DhalDMD_INTERN_common.h113 #define T2FDP_REG_BASE 0x3100 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mustang/demod/
H A DhalDMD_INTERN_DVBT2.c437 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x17*2)+1, &u8Data); in INTERN_DVBT2_SoftReset()
438 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+(0x17*2)+1, (u8Data|0x10)); in INTERN_DVBT2_SoftReset()
440 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+0xff, 0x10); in INTERN_DVBT2_SoftReset()
464 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x18*2), &u8Data); in INTERN_DVBT2_SoftReset()
2157 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+0x01*2, &reg); in INTERN_DVBT2_GetSNR()
H A DhalDMD_INTERN_common.h110 #define T2FDP_REG_BASE 0x3100 macro