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Searched refs:T2DJB_REG_BASE (Results 1 – 24 of 24) sorted by relevance

/utopia/UTPA2-700.0.x/modules/demodulator/hal/manhattan/demod/
H A DhalDMD_INTERN_DVBT2.c430 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2), &u8Data); in INTERN_DVBT2_SoftReset()
431 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE+(0x65*2), (u8Data|0x01)); in INTERN_DVBT2_SoftReset()
2011 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2019 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x01) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2023 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2), 0x16) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2027 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2031 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x00) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
H A DhalDMD_INTERN_common.h117 #define T2DJB_REG_BASE 0x2d00 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/macan/demod/
H A DhalDMD_INTERN_DVBT2.c439 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2), &u8Data); in INTERN_DVBT2_SoftReset()
440 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE+(0x65*2), (u8Data|0x01)); in INTERN_DVBT2_SoftReset()
2045 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2053 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x01) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2057 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2), 0x16) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2061 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2065 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x00) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
H A DhalDMD_INTERN_common.h118 #define T2DJB_REG_BASE 0x2d00 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mustang/demod/
H A DhalDMD_INTERN_DVBT2.c444 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2), &u8Data); in INTERN_DVBT2_SoftReset()
445 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE+(0x65*2), (u8Data|0x01)); in INTERN_DVBT2_SoftReset()
2052 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2060 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x01) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2064 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2), 0x16) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2068 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2072 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x00) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
H A DhalDMD_INTERN_common.h115 #define T2DJB_REG_BASE 0x2d00 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maserati/demod/
H A DhalDMD_INTERN_DVBT2.c436 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2), &u8Data); in INTERN_DVBT2_SoftReset()
437 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE+(0x65*2), (u8Data|0x01)); in INTERN_DVBT2_SoftReset()
2108 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2116 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x01) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2120 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2), 0x16) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2124 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2128 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x00) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
H A DhalDMD_INTERN_common.h117 #define T2DJB_REG_BASE 0x2d00 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/kano/demod/
H A DhalDMD_INTERN_DVBT2.c436 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2), &u8Data); in INTERN_DVBT2_SoftReset()
437 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE+(0x65*2), (u8Data|0x01)); in INTERN_DVBT2_SoftReset()
2108 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2116 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x01) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2120 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2), 0x16) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2124 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2128 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x00) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
H A DhalDMD_INTERN_common.h117 #define T2DJB_REG_BASE 0x2d00 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7621/demod/
H A DhalDMD_INTERN_DVBT2.c449 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2), &u8Data); in INTERN_DVBT2_SoftReset()
450 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE+(0x65*2), (u8Data|0x01)); in INTERN_DVBT2_SoftReset()
2156 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2164 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x01) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2168 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2), 0x16) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2172 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2176 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x00) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
H A DhalDMD_INTERN_common.h118 #define T2DJB_REG_BASE 0x2d00 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6/demod/
H A DhalDMD_INTERN_DVBT2.c436 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2), &u8Data); in INTERN_DVBT2_SoftReset()
437 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE+(0x65*2), (u8Data|0x01)); in INTERN_DVBT2_SoftReset()
2108 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2116 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x01) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2120 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2), 0x16) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2124 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2128 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x00) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
H A DhalDMD_INTERN_common.h117 #define T2DJB_REG_BASE 0x2d00 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/curry/demod/
H A DhalDMD_INTERN_DVBT2.c436 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2), &u8Data); in INTERN_DVBT2_SoftReset()
437 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE+(0x65*2), (u8Data|0x01)); in INTERN_DVBT2_SoftReset()
2108 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2116 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x01) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2120 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2), 0x16) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2124 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2128 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x00) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
H A DhalDMD_INTERN_common.h117 #define T2DJB_REG_BASE 0x2d00 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6lite/demod/
H A DhalDMD_INTERN_DVBT2.c436 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2), &u8Data); in INTERN_DVBT2_SoftReset()
437 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE+(0x65*2), (u8Data|0x01)); in INTERN_DVBT2_SoftReset()
2108 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2116 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x01) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2120 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2), 0x16) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2124 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2128 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x00) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
H A DhalDMD_INTERN_common.h118 #define T2DJB_REG_BASE 0x2d00 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7821/demod/
H A DhalDMD_INTERN_DVBT2.c436 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2), &u8Data); in INTERN_DVBT2_SoftReset()
437 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE+(0x65*2), (u8Data|0x01)); in INTERN_DVBT2_SoftReset()
2108 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2116 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x01) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2120 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2), 0x16) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2124 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2128 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x00) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
H A DhalDMD_INTERN_common.h117 #define T2DJB_REG_BASE 0x2d00 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maxim/demod/
H A DhalDMD_INTERN_DVBT2.c449 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2), &u8Data); in INTERN_DVBT2_SoftReset()
450 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE+(0x65*2), (u8Data|0x01)); in INTERN_DVBT2_SoftReset()
2156 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2164 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x01) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2168 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2), 0x16) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2172 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
2176 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x00) == FALSE) in INTERN_DVBT2_Get_L1_Parameter()
H A DhalDMD_INTERN_common.h118 #define T2DJB_REG_BASE 0x2d00 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maldives/demod/
H A DhalDMD_INTERN_common.h114 #define T2DJB_REG_BASE 0x2d00 macro
H A DhalDMD_INTERN_DVBT2.c419 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2), &u8Data); in INTERN_DVBT2_SoftReset()
420 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE+(0x65*2), (u8Data|0x01)); in INTERN_DVBT2_SoftReset()