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Searched refs:REG_INT_AEONFIRE (Results 1 – 25 of 30) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/mbx/hal/k6/mbx/
H A DhalMBXINT.c309 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H2; in MHAL_MBXINT_Fire()
310 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H2; in MHAL_MBXINT_Fire()
343 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
344 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
352 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H3; in MHAL_MBXINT_Fire()
353 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H3); in MHAL_MBXINT_Fire()
H A DregMBXINT.h153 #define REG_INT_AEONFIRE 0x0002 macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/curry/mbx/
H A DhalMBXINT.c309 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H2; in MHAL_MBXINT_Fire()
310 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H2; in MHAL_MBXINT_Fire()
343 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
344 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
352 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H3; in MHAL_MBXINT_Fire()
353 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H3); in MHAL_MBXINT_Fire()
H A DregMBXINT.h153 #define REG_INT_AEONFIRE 0x0002 macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/k6lite/mbx/
H A DhalMBXINT.c309 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H2; in MHAL_MBXINT_Fire()
310 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H2; in MHAL_MBXINT_Fire()
343 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
344 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
352 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H3; in MHAL_MBXINT_Fire()
353 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H3); in MHAL_MBXINT_Fire()
H A DregMBXINT.h153 #define REG_INT_AEONFIRE 0x0002 macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/kano/mbx/
H A DhalMBXINT.c309 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H2; in MHAL_MBXINT_Fire()
310 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H2; in MHAL_MBXINT_Fire()
343 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
344 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
352 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H3; in MHAL_MBXINT_Fire()
353 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H3); in MHAL_MBXINT_Fire()
H A DregMBXINT.h153 #define REG_INT_AEONFIRE 0x0002 macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/mooney/mbx/
H A DhalMBXINT.c304 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
305 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H1; in MHAL_MBXINT_Fire()
343 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
344 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
352 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
353 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H1); in MHAL_MBXINT_Fire()
H A DregMBXINT.h150 #define REG_INT_AEONFIRE 0x0006 //AMR0 macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/maldives/mbx/
H A DhalMBXINT.c303 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H2; in MHAL_MBXINT_Fire()
304 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H2; in MHAL_MBXINT_Fire()
341 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
342 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
350 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H2; in MHAL_MBXINT_Fire()
351 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H2); in MHAL_MBXINT_Fire()
H A DregMBXINT.h143 #define REG_INT_AEONFIRE 0x0002 //R2 macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/macan/mbx/
H A DhalMBXINT.c310 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
311 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H1; in MHAL_MBXINT_Fire()
342 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
343 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
351 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
352 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H1); in MHAL_MBXINT_Fire()
/utopia/UTPA2-700.0.x/modules/mbx/hal/messi/mbx/
H A DhalMBXINT.c306 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
307 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H1; in MHAL_MBXINT_Fire()
345 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
346 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
354 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
355 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H1); in MHAL_MBXINT_Fire()
H A DregMBXINT.h150 #define REG_INT_AEONFIRE 0x0006 //AMR0 macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/mustang/mbx/
H A DhalMBXINT.c303 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H2; in MHAL_MBXINT_Fire()
304 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H2; in MHAL_MBXINT_Fire()
341 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
342 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
350 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H2; in MHAL_MBXINT_Fire()
351 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H2); in MHAL_MBXINT_Fire()
H A DregMBXINT.h143 #define REG_INT_AEONFIRE 0x0002 //R2 macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/mainz/mbx/
H A DhalMBXINT.c306 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
307 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H1; in MHAL_MBXINT_Fire()
345 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
346 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
354 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
355 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H1); in MHAL_MBXINT_Fire()
H A DregMBXINT.h150 #define REG_INT_AEONFIRE 0x0006 //AMR0 macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/M7821/mbx/
H A DhalMBXINT.c342 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
343 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H1; in MHAL_MBXINT_Fire()
395 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
396 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
404 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
405 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H1); in MHAL_MBXINT_Fire()
/utopia/UTPA2-700.0.x/modules/mbx/hal/manhattan/mbx/
H A DhalMBXINT.c342 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
343 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H1; in MHAL_MBXINT_Fire()
395 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
396 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
404 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
405 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H1); in MHAL_MBXINT_Fire()
H A DregMBXINT.h175 #define REG_INT_AEONFIRE 0x0006 //AMR0 macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/maxim/mbx/
H A DhalMBXINT.c342 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
343 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H1; in MHAL_MBXINT_Fire()
395 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
396 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
404 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
405 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H1); in MHAL_MBXINT_Fire()
/utopia/UTPA2-700.0.x/modules/mbx/hal/maserati/mbx/
H A DhalMBXINT.c342 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
343 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H1; in MHAL_MBXINT_Fire()
395 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
396 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
404 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
405 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H1); in MHAL_MBXINT_Fire()
/utopia/UTPA2-700.0.x/modules/mbx/hal/M7621/mbx/
H A DhalMBXINT.c342 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
343 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H1; in MHAL_MBXINT_Fire()
395 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
396 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
404 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1; in MHAL_MBXINT_Fire()
405 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H1); in MHAL_MBXINT_Fire()

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