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Searched refs:REG_HVD_BASE (Results 1 – 25 of 82) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maserati/hvd/
H A DregHVD.h221 #define REG_HVD_BASE (0x1B00) macro
223 #define HVD_REG_REV_ID (REG_HVD_BASE+(( 0x0000)<<1))
224 #define HVD_REG_RESET (REG_HVD_BASE+(( 0x0001)<<1))
233 #define HVD_REG_ESB_ST_ADDR_L (REG_HVD_BASE+(( 0x0002)<<1))
234 #define HVD_REG_ESB_ST_ADDR_H (REG_HVD_BASE+(( 0x0003)<<1))
236 #define HVD_REG_ESB_LENGTH_L (REG_HVD_BASE+(( 0x0004)<<1))
237 #define HVD_REG_ESB_LENGTH_H (REG_HVD_BASE+(( 0x0005)<<1))
239 #define HVD_REG_ESB_RPTR (REG_HVD_BASE+(( 0x0006)<<1))
244 #define HVD_REG_ESB_RPTR_H (REG_HVD_BASE+(( 0x0007)<<1))
245 #define HVD_REG_MIF_BBU (REG_HVD_BASE+(( 0x0008)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/manhattan/hvd/
H A DregHVD.h221 #define REG_HVD_BASE (0x1B00) macro
223 #define HVD_REG_REV_ID (REG_HVD_BASE+(( 0x0000)<<1))
224 #define HVD_REG_RESET (REG_HVD_BASE+(( 0x0001)<<1))
233 #define HVD_REG_ESB_ST_ADDR_L (REG_HVD_BASE+(( 0x0002)<<1))
234 #define HVD_REG_ESB_ST_ADDR_H (REG_HVD_BASE+(( 0x0003)<<1))
236 #define HVD_REG_ESB_LENGTH_L (REG_HVD_BASE+(( 0x0004)<<1))
237 #define HVD_REG_ESB_LENGTH_H (REG_HVD_BASE+(( 0x0005)<<1))
239 #define HVD_REG_ESB_RPTR (REG_HVD_BASE+(( 0x0006)<<1))
244 #define HVD_REG_ESB_RPTR_H (REG_HVD_BASE+(( 0x0007)<<1))
245 #define HVD_REG_MIF_BBU (REG_HVD_BASE+(( 0x0008)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/macan/hvd/
H A DregHVD.h221 #define REG_HVD_BASE (0x1B00) macro
223 #define HVD_REG_REV_ID (REG_HVD_BASE+(( 0x0000)<<1))
224 #define HVD_REG_RESET (REG_HVD_BASE+(( 0x0001)<<1))
233 #define HVD_REG_ESB_ST_ADDR_L (REG_HVD_BASE+(( 0x0002)<<1))
234 #define HVD_REG_ESB_ST_ADDR_H (REG_HVD_BASE+(( 0x0003)<<1))
236 #define HVD_REG_ESB_LENGTH_L (REG_HVD_BASE+(( 0x0004)<<1))
237 #define HVD_REG_ESB_LENGTH_H (REG_HVD_BASE+(( 0x0005)<<1))
239 #define HVD_REG_ESB_RPTR (REG_HVD_BASE+(( 0x0006)<<1))
244 #define HVD_REG_ESB_RPTR_H (REG_HVD_BASE+(( 0x0007)<<1))
245 #define HVD_REG_MIF_BBU (REG_HVD_BASE+(( 0x0008)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7821/hvd/
H A DregHVD.h221 #define REG_HVD_BASE (0x1B00) macro
223 #define HVD_REG_REV_ID (REG_HVD_BASE+(( 0x0000)<<1))
224 #define HVD_REG_RESET (REG_HVD_BASE+(( 0x0001)<<1))
233 #define HVD_REG_ESB_ST_ADDR_L (REG_HVD_BASE+(( 0x0002)<<1))
234 #define HVD_REG_ESB_ST_ADDR_H (REG_HVD_BASE+(( 0x0003)<<1))
236 #define HVD_REG_ESB_LENGTH_L (REG_HVD_BASE+(( 0x0004)<<1))
237 #define HVD_REG_ESB_LENGTH_H (REG_HVD_BASE+(( 0x0005)<<1))
239 #define HVD_REG_ESB_RPTR (REG_HVD_BASE+(( 0x0006)<<1))
244 #define HVD_REG_ESB_RPTR_H (REG_HVD_BASE+(( 0x0007)<<1))
245 #define HVD_REG_MIF_BBU (REG_HVD_BASE+(( 0x0008)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maxim/hvd/
H A DregHVD.h221 #define REG_HVD_BASE (0x1B00) macro
223 #define HVD_REG_REV_ID (REG_HVD_BASE+(( 0x0000)<<1))
224 #define HVD_REG_RESET (REG_HVD_BASE+(( 0x0001)<<1))
233 #define HVD_REG_ESB_ST_ADDR_L (REG_HVD_BASE+(( 0x0002)<<1))
234 #define HVD_REG_ESB_ST_ADDR_H (REG_HVD_BASE+(( 0x0003)<<1))
236 #define HVD_REG_ESB_LENGTH_L (REG_HVD_BASE+(( 0x0004)<<1))
237 #define HVD_REG_ESB_LENGTH_H (REG_HVD_BASE+(( 0x0005)<<1))
239 #define HVD_REG_ESB_RPTR (REG_HVD_BASE+(( 0x0006)<<1))
244 #define HVD_REG_ESB_RPTR_H (REG_HVD_BASE+(( 0x0007)<<1))
245 #define HVD_REG_MIF_BBU (REG_HVD_BASE+(( 0x0008)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7621/hvd/
H A DregHVD.h221 #define REG_HVD_BASE (0x1B00) macro
223 #define HVD_REG_REV_ID (REG_HVD_BASE+(( 0x0000)<<1))
224 #define HVD_REG_RESET (REG_HVD_BASE+(( 0x0001)<<1))
233 #define HVD_REG_ESB_ST_ADDR_L (REG_HVD_BASE+(( 0x0002)<<1))
234 #define HVD_REG_ESB_ST_ADDR_H (REG_HVD_BASE+(( 0x0003)<<1))
236 #define HVD_REG_ESB_LENGTH_L (REG_HVD_BASE+(( 0x0004)<<1))
237 #define HVD_REG_ESB_LENGTH_H (REG_HVD_BASE+(( 0x0005)<<1))
239 #define HVD_REG_ESB_RPTR (REG_HVD_BASE+(( 0x0006)<<1))
244 #define HVD_REG_ESB_RPTR_H (REG_HVD_BASE+(( 0x0007)<<1))
245 #define HVD_REG_MIF_BBU (REG_HVD_BASE+(( 0x0008)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mustang/hvd_ex/
H A DregHVD_EX.h231 #define REG_HVD_BASE (0x1B00) macro
234 #define HVD_REG_REV_ID (REG_HVD_BASE + ((0x0000) << 1))
235 #define HVD_REG_RESET (REG_HVD_BASE + ((0x0001) << 1))
309 #define HVD_REG_DEBUG_DAT_L (REG_HVD_BASE + ((0x0023) << 1))
310 #define HVD_REG_DEBUG_DAT_H (REG_HVD_BASE + ((0x0024) << 1))
311 #define HVD_REG_DEBUG_SEL (REG_HVD_BASE + ((0x0025) << 1))
314 #define HVD_REG_MODE_BS2 (REG_HVD_BASE + ((0x0030) << 1))
319 #define HVD_REG_ESB_ST_ADDR_L_BS2 (REG_HVD_BASE + ((0x0032) << 1))
320 #define HVD_REG_ESB_ST_ADDR_H_BS2 (REG_HVD_BASE + ((0x0033) << 1))
322 #define HVD_REG_ESB_LENGTH_L_BS2 (REG_HVD_BASE + ((0x0034) << 1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maldives/hvd_ex/
H A DregHVD_EX.h231 #define REG_HVD_BASE (0x1B00) macro
234 #define HVD_REG_REV_ID (REG_HVD_BASE + ((0x0000) << 1))
235 #define HVD_REG_RESET (REG_HVD_BASE + ((0x0001) << 1))
309 #define HVD_REG_DEBUG_DAT_L (REG_HVD_BASE + ((0x0023) << 1))
310 #define HVD_REG_DEBUG_DAT_H (REG_HVD_BASE + ((0x0024) << 1))
311 #define HVD_REG_DEBUG_SEL (REG_HVD_BASE + ((0x0025) << 1))
314 #define HVD_REG_MODE_BS2 (REG_HVD_BASE + ((0x0030) << 1))
319 #define HVD_REG_ESB_ST_ADDR_L_BS2 (REG_HVD_BASE + ((0x0032) << 1))
320 #define HVD_REG_ESB_ST_ADDR_H_BS2 (REG_HVD_BASE + ((0x0033) << 1))
322 #define HVD_REG_ESB_LENGTH_L_BS2 (REG_HVD_BASE + ((0x0034) << 1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7621/hvd_ex/
H A DregHVD_EX.h221 #define REG_HVD_BASE (0x1B00) macro
224 #define HVD_REG_REV_ID (REG_HVD_BASE + ((0x0000) << 1))
225 #define HVD_REG_RESET (REG_HVD_BASE + ((0x0001) << 1))
298 #define HVD_REG_DEBUG_DAT_L (REG_HVD_BASE + ((0x0023) << 1))
299 #define HVD_REG_DEBUG_DAT_H (REG_HVD_BASE + ((0x0024) << 1))
300 #define HVD_REG_DEBUG_SEL (REG_HVD_BASE + ((0x0025) << 1))
303 #define HVD_REG_MODE_BS2 (REG_HVD_BASE + ((0x0030) << 1))
308 #define HVD_REG_ESB_ST_ADDR_L_BS2 (REG_HVD_BASE + ((0x0032) << 1))
309 #define HVD_REG_ESB_ST_ADDR_H_BS2 (REG_HVD_BASE + ((0x0033) << 1))
311 #define HVD_REG_ESB_LENGTH_L_BS2 (REG_HVD_BASE + ((0x0034) << 1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/messi/hvd_ex/
H A DregHVD_EX.h221 #define REG_HVD_BASE (0x1B00) macro
224 #define HVD_REG_REV_ID (REG_HVD_BASE + ((0x0000) << 1))
225 #define HVD_REG_RESET (REG_HVD_BASE + ((0x0001) << 1))
298 #define HVD_REG_DEBUG_DAT_L (REG_HVD_BASE + ((0x0023) << 1))
299 #define HVD_REG_DEBUG_DAT_H (REG_HVD_BASE + ((0x0024) << 1))
300 #define HVD_REG_DEBUG_SEL (REG_HVD_BASE + ((0x0025) << 1))
303 #define HVD_REG_MODE_BS2 (REG_HVD_BASE + ((0x0030) << 1))
308 #define HVD_REG_ESB_ST_ADDR_L_BS2 (REG_HVD_BASE + ((0x0032) << 1))
309 #define HVD_REG_ESB_ST_ADDR_H_BS2 (REG_HVD_BASE + ((0x0033) << 1))
311 #define HVD_REG_ESB_LENGTH_L_BS2 (REG_HVD_BASE + ((0x0034) << 1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/manhattan/hvd_ex/
H A DregHVD_EX.h221 #define REG_HVD_BASE (0x1B00) macro
224 #define HVD_REG_REV_ID (REG_HVD_BASE + ((0x0000) << 1))
225 #define HVD_REG_RESET (REG_HVD_BASE + ((0x0001) << 1))
298 #define HVD_REG_DEBUG_DAT_L (REG_HVD_BASE + ((0x0023) << 1))
299 #define HVD_REG_DEBUG_DAT_H (REG_HVD_BASE + ((0x0024) << 1))
300 #define HVD_REG_DEBUG_SEL (REG_HVD_BASE + ((0x0025) << 1))
303 #define HVD_REG_MODE_BS2 (REG_HVD_BASE + ((0x0030) << 1))
308 #define HVD_REG_ESB_ST_ADDR_L_BS2 (REG_HVD_BASE + ((0x0032) << 1))
309 #define HVD_REG_ESB_ST_ADDR_H_BS2 (REG_HVD_BASE + ((0x0033) << 1))
311 #define HVD_REG_ESB_LENGTH_L_BS2 (REG_HVD_BASE + ((0x0034) << 1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maxim/hvd_ex/
H A DregHVD_EX.h221 #define REG_HVD_BASE (0x1B00) macro
224 #define HVD_REG_REV_ID (REG_HVD_BASE + ((0x0000) << 1))
225 #define HVD_REG_RESET (REG_HVD_BASE + ((0x0001) << 1))
298 #define HVD_REG_DEBUG_DAT_L (REG_HVD_BASE + ((0x0023) << 1))
299 #define HVD_REG_DEBUG_DAT_H (REG_HVD_BASE + ((0x0024) << 1))
300 #define HVD_REG_DEBUG_SEL (REG_HVD_BASE + ((0x0025) << 1))
303 #define HVD_REG_MODE_BS2 (REG_HVD_BASE + ((0x0030) << 1))
308 #define HVD_REG_ESB_ST_ADDR_L_BS2 (REG_HVD_BASE + ((0x0032) << 1))
309 #define HVD_REG_ESB_ST_ADDR_H_BS2 (REG_HVD_BASE + ((0x0033) << 1))
311 #define HVD_REG_ESB_LENGTH_L_BS2 (REG_HVD_BASE + ((0x0034) << 1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mainz/hvd_ex/
H A DregHVD_EX.h221 #define REG_HVD_BASE (0x1B00) macro
224 #define HVD_REG_REV_ID (REG_HVD_BASE + ((0x0000) << 1))
225 #define HVD_REG_RESET (REG_HVD_BASE + ((0x0001) << 1))
298 #define HVD_REG_DEBUG_DAT_L (REG_HVD_BASE + ((0x0023) << 1))
299 #define HVD_REG_DEBUG_DAT_H (REG_HVD_BASE + ((0x0024) << 1))
300 #define HVD_REG_DEBUG_SEL (REG_HVD_BASE + ((0x0025) << 1))
303 #define HVD_REG_MODE_BS2 (REG_HVD_BASE + ((0x0030) << 1))
308 #define HVD_REG_ESB_ST_ADDR_L_BS2 (REG_HVD_BASE + ((0x0032) << 1))
309 #define HVD_REG_ESB_ST_ADDR_H_BS2 (REG_HVD_BASE + ((0x0033) << 1))
311 #define HVD_REG_ESB_LENGTH_L_BS2 (REG_HVD_BASE + ((0x0034) << 1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maserati/hvd_ex/
H A DregHVD_EX.h221 #define REG_HVD_BASE (0x1B00) macro
224 #define HVD_REG_REV_ID (REG_HVD_BASE + ((0x0000) << 1))
225 #define HVD_REG_RESET (REG_HVD_BASE + ((0x0001) << 1))
298 #define HVD_REG_DEBUG_DAT_L (REG_HVD_BASE + ((0x0023) << 1))
299 #define HVD_REG_DEBUG_DAT_H (REG_HVD_BASE + ((0x0024) << 1))
300 #define HVD_REG_DEBUG_SEL (REG_HVD_BASE + ((0x0025) << 1))
303 #define HVD_REG_MODE_BS2 (REG_HVD_BASE + ((0x0030) << 1))
308 #define HVD_REG_ESB_ST_ADDR_L_BS2 (REG_HVD_BASE + ((0x0032) << 1))
309 #define HVD_REG_ESB_ST_ADDR_H_BS2 (REG_HVD_BASE + ((0x0033) << 1))
311 #define HVD_REG_ESB_LENGTH_L_BS2 (REG_HVD_BASE + ((0x0034) << 1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7821/hvd_ex/
H A DregHVD_EX.h221 #define REG_HVD_BASE (0x1B00) macro
224 #define HVD_REG_REV_ID (REG_HVD_BASE + ((0x0000) << 1))
225 #define HVD_REG_RESET (REG_HVD_BASE + ((0x0001) << 1))
298 #define HVD_REG_DEBUG_DAT_L (REG_HVD_BASE + ((0x0023) << 1))
299 #define HVD_REG_DEBUG_DAT_H (REG_HVD_BASE + ((0x0024) << 1))
300 #define HVD_REG_DEBUG_SEL (REG_HVD_BASE + ((0x0025) << 1))
303 #define HVD_REG_MODE_BS2 (REG_HVD_BASE + ((0x0030) << 1))
308 #define HVD_REG_ESB_ST_ADDR_L_BS2 (REG_HVD_BASE + ((0x0032) << 1))
309 #define HVD_REG_ESB_ST_ADDR_H_BS2 (REG_HVD_BASE + ((0x0033) << 1))
311 #define HVD_REG_ESB_LENGTH_L_BS2 (REG_HVD_BASE + ((0x0034) << 1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/macan/hvd_ex/
H A DregHVD_EX.h221 #define REG_HVD_BASE (0x1B00) macro
224 #define HVD_REG_REV_ID (REG_HVD_BASE + ((0x0000) << 1))
225 #define HVD_REG_RESET (REG_HVD_BASE + ((0x0001) << 1))
298 #define HVD_REG_DEBUG_DAT_L (REG_HVD_BASE + ((0x0023) << 1))
299 #define HVD_REG_DEBUG_DAT_H (REG_HVD_BASE + ((0x0024) << 1))
300 #define HVD_REG_DEBUG_SEL (REG_HVD_BASE + ((0x0025) << 1))
303 #define HVD_REG_MODE_BS2 (REG_HVD_BASE + ((0x0030) << 1))
308 #define HVD_REG_ESB_ST_ADDR_L_BS2 (REG_HVD_BASE + ((0x0032) << 1))
309 #define HVD_REG_ESB_ST_ADDR_H_BS2 (REG_HVD_BASE + ((0x0033) << 1))
311 #define HVD_REG_ESB_LENGTH_L_BS2 (REG_HVD_BASE + ((0x0034) << 1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maldives/hvd_v3/
H A DregHVD_EX.h231 #define REG_HVD_BASE (0x1B00) macro
234 #define HVD_REG_REV_ID (REG_HVD_BASE + ((0x0000) << 1))
235 #define HVD_REG_RESET (REG_HVD_BASE + ((0x0001) << 1))
309 #define HVD_REG_DEBUG_DAT_L (REG_HVD_BASE + ((0x0023) << 1))
310 #define HVD_REG_DEBUG_DAT_H (REG_HVD_BASE + ((0x0024) << 1))
311 #define HVD_REG_DEBUG_SEL (REG_HVD_BASE + ((0x0025) << 1))
314 #define HVD_REG_MODE_BS2 (REG_HVD_BASE + ((0x0030) << 1))
345 #define HVD_REG_ESB_WPTR_L_BS2 (REG_HVD_BASE + ((0x003E) << 1))
346 #define HVD_REG_ESB_WPTR_H_BS2 (REG_HVD_BASE + ((0x003F) << 1))
349 #define HVD_REG_HK_VP8 (REG_HVD_BASE + ((0x0040) << 1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mustang/hvd_v3/
H A DregHVD_EX.h231 #define REG_HVD_BASE (0x1B00) macro
234 #define HVD_REG_REV_ID (REG_HVD_BASE + ((0x0000) << 1))
235 #define HVD_REG_RESET (REG_HVD_BASE + ((0x0001) << 1))
313 #define HVD_REG_DEBUG_DAT_L (REG_HVD_BASE + ((0x0023) << 1))
314 #define HVD_REG_DEBUG_DAT_H (REG_HVD_BASE + ((0x0024) << 1))
315 #define HVD_REG_DEBUG_SEL (REG_HVD_BASE + ((0x0025) << 1))
318 #define HVD_REG_MODE_BS2 (REG_HVD_BASE + ((0x0030) << 1))
349 #define HVD_REG_ESB_WPTR_L_BS2 (REG_HVD_BASE + ((0x003E) << 1))
350 #define HVD_REG_ESB_WPTR_H_BS2 (REG_HVD_BASE + ((0x003F) << 1))
353 #define HVD_REG_HK_VP8 (REG_HVD_BASE + ((0x0040) << 1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/hvd_v3/
H A DregHVD_EX.h231 #define REG_HVD_BASE (0x1B00) macro
235 #define HVD_REG_REV_ID (REG_HVD_BASE + ((0x0000) << 1))
236 #define HVD_REG_RESET (REG_HVD_BASE + ((0x0001) << 1))
314 #define HVD_REG_DEBUG_DAT_L (REG_HVD_BASE + ((0x0023) << 1))
315 #define HVD_REG_DEBUG_DAT_H (REG_HVD_BASE + ((0x0024) << 1))
316 #define HVD_REG_DEBUG_SEL (REG_HVD_BASE + ((0x0025) << 1))
319 #define HVD_REG_MODE_BS2 (REG_HVD_BASE + ((0x0030) << 1))
350 #define HVD_REG_ESB_WPTR_L_BS2 (REG_HVD_BASE + ((0x003E) << 1))
351 #define HVD_REG_ESB_WPTR_H_BS2 (REG_HVD_BASE + ((0x003F) << 1))
354 #define HVD_REG_HK_VP8 (REG_HVD_BASE + ((0x0040) << 1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/hvd_v3/
H A DregHVD_EX.h231 #define REG_HVD_BASE (0x1B00) macro
235 #define HVD_REG_REV_ID (REG_HVD_BASE + ((0x0000) << 1))
236 #define HVD_REG_RESET (REG_HVD_BASE + ((0x0001) << 1))
313 #define HVD_REG_DEBUG_DAT_L (REG_HVD_BASE + ((0x0023) << 1))
314 #define HVD_REG_DEBUG_DAT_H (REG_HVD_BASE + ((0x0024) << 1))
315 #define HVD_REG_DEBUG_SEL (REG_HVD_BASE + ((0x0025) << 1))
318 #define HVD_REG_MODE_BS2 (REG_HVD_BASE + ((0x0030) << 1))
349 #define HVD_REG_ESB_WPTR_L_BS2 (REG_HVD_BASE + ((0x003E) << 1))
350 #define HVD_REG_ESB_WPTR_H_BS2 (REG_HVD_BASE + ((0x003F) << 1))
353 #define HVD_REG_HK_VP8 (REG_HVD_BASE + ((0x0040) << 1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/hvd_v3/
H A DregHVD_EX.h231 #define REG_HVD_BASE (0x1B00) macro
235 #define HVD_REG_REV_ID (REG_HVD_BASE + ((0x0000) << 1))
236 #define HVD_REG_RESET (REG_HVD_BASE + ((0x0001) << 1))
314 #define HVD_REG_DEBUG_DAT_L (REG_HVD_BASE + ((0x0023) << 1))
315 #define HVD_REG_DEBUG_DAT_H (REG_HVD_BASE + ((0x0024) << 1))
316 #define HVD_REG_DEBUG_SEL (REG_HVD_BASE + ((0x0025) << 1))
319 #define HVD_REG_MODE_BS2 (REG_HVD_BASE + ((0x0030) << 1))
350 #define HVD_REG_ESB_WPTR_L_BS2 (REG_HVD_BASE + ((0x003E) << 1))
351 #define HVD_REG_ESB_WPTR_H_BS2 (REG_HVD_BASE + ((0x003F) << 1))
354 #define HVD_REG_HK_VP8 (REG_HVD_BASE + ((0x0040) << 1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/hvd_v3/
H A DregHVD_EX.h231 #define REG_HVD_BASE (0x1B00) macro
235 #define HVD_REG_REV_ID (REG_HVD_BASE + ((0x0000) << 1))
236 #define HVD_REG_RESET (REG_HVD_BASE + ((0x0001) << 1))
314 #define HVD_REG_DEBUG_DAT_L (REG_HVD_BASE + ((0x0023) << 1))
315 #define HVD_REG_DEBUG_DAT_H (REG_HVD_BASE + ((0x0024) << 1))
316 #define HVD_REG_DEBUG_SEL (REG_HVD_BASE + ((0x0025) << 1))
319 #define HVD_REG_MODE_BS2 (REG_HVD_BASE + ((0x0030) << 1))
350 #define HVD_REG_ESB_WPTR_L_BS2 (REG_HVD_BASE + ((0x003E) << 1))
351 #define HVD_REG_ESB_WPTR_H_BS2 (REG_HVD_BASE + ((0x003F) << 1))
354 #define HVD_REG_HK_VP8 (REG_HVD_BASE + ((0x0040) << 1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/hvd_v3/
H A DregHVD_EX.h231 #define REG_HVD_BASE (0x1B00) macro
235 #define HVD_REG_REV_ID (REG_HVD_BASE + ((0x0000) << 1))
236 #define HVD_REG_RESET (REG_HVD_BASE + ((0x0001) << 1))
314 #define HVD_REG_DEBUG_DAT_L (REG_HVD_BASE + ((0x0023) << 1))
315 #define HVD_REG_DEBUG_DAT_H (REG_HVD_BASE + ((0x0024) << 1))
316 #define HVD_REG_DEBUG_SEL (REG_HVD_BASE + ((0x0025) << 1))
319 #define HVD_REG_MODE_BS2 (REG_HVD_BASE + ((0x0030) << 1))
350 #define HVD_REG_ESB_WPTR_L_BS2 (REG_HVD_BASE + ((0x003E) << 1))
351 #define HVD_REG_ESB_WPTR_H_BS2 (REG_HVD_BASE + ((0x003F) << 1))
354 #define HVD_REG_HK_VP8 (REG_HVD_BASE + ((0x0040) << 1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/hvd_v3/
H A DregHVD_EX.h231 #define REG_HVD_BASE (0x1B00) macro
235 #define HVD_REG_REV_ID (REG_HVD_BASE + ((0x0000) << 1))
236 #define HVD_REG_RESET (REG_HVD_BASE + ((0x0001) << 1))
314 #define HVD_REG_DEBUG_DAT_L (REG_HVD_BASE + ((0x0023) << 1))
315 #define HVD_REG_DEBUG_DAT_H (REG_HVD_BASE + ((0x0024) << 1))
316 #define HVD_REG_DEBUG_SEL (REG_HVD_BASE + ((0x0025) << 1))
319 #define HVD_REG_MODE_BS2 (REG_HVD_BASE + ((0x0030) << 1))
350 #define HVD_REG_ESB_WPTR_L_BS2 (REG_HVD_BASE + ((0x003E) << 1))
351 #define HVD_REG_ESB_WPTR_H_BS2 (REG_HVD_BASE + ((0x003F) << 1))
354 #define HVD_REG_HK_VP8 (REG_HVD_BASE + ((0x0040) << 1))
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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/hvd_v3/
H A DregHVD_EX.h231 #define REG_HVD_BASE (0x1B00) macro
235 #define HVD_REG_REV_ID (REG_HVD_BASE + ((0x0000) << 1))
236 #define HVD_REG_RESET (REG_HVD_BASE + ((0x0001) << 1))
313 #define HVD_REG_DEBUG_DAT_L (REG_HVD_BASE + ((0x0023) << 1))
314 #define HVD_REG_DEBUG_DAT_H (REG_HVD_BASE + ((0x0024) << 1))
315 #define HVD_REG_DEBUG_SEL (REG_HVD_BASE + ((0x0025) << 1))
318 #define HVD_REG_MODE_BS2 (REG_HVD_BASE + ((0x0030) << 1))
349 #define HVD_REG_ESB_WPTR_L_BS2 (REG_HVD_BASE + ((0x003E) << 1))
350 #define HVD_REG_ESB_WPTR_H_BS2 (REG_HVD_BASE + ((0x003F) << 1))
353 #define HVD_REG_HK_VP8 (REG_HVD_BASE + ((0x0040) << 1))
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