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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file regHVD.h 98 /// @brief HVD Module Register Definition 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_HVD_H_ 103 #define _REG_HVD_H_ 104 105 106 //------------------------------------------------------------------------------------------------- 107 // Hardware Capability 108 //------------------------------------------------------------------------------------------------- 109 110 111 //------------------------------------------------------------------------------------------------- 112 // Macro and Define 113 //------------------------------------------------------------------------------------------------- 114 115 //***************************************************************************** 116 // RIU macro 117 #define HVD_MACRO_START do { 118 #define HVD_MACRO_END } while (0) 119 #define HVD_RIU_BASE u32HVDRegOSBase 120 121 #define HVD_HIGHBYTE(u16) ((MS_U8)((u16) >> 8)) 122 #define HVD_LOWBYTE(u16) ((MS_U8)(u16)) 123 #define HVD_RIU_READ_BYTE(addr) ( READ_BYTE( HVD_RIU_BASE + (addr) ) ) 124 #define HVD_RIU_READ_WORD(addr) ( READ_WORD( HVD_RIU_BASE + (addr) ) ) 125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } 126 #define HVD_RIU_WRITE_WORD(addr, val) { WRITE_WORD( HVD_RIU_BASE+(addr), val); } 127 128 129 #define _HVD_ReadByte( u32Reg ) HVD_RIU_READ_BYTE(((u32Reg) << 1) - ((u32Reg) & 1)) 130 131 #define _HVD_Read2Byte( u32Reg ) (HVD_RIU_READ_WORD((u32Reg)<<1)) 132 133 #define _HVD_Read4Byte( u32Reg ) ( (MS_U32)HVD_RIU_READ_WORD((u32Reg)<<1) | ((MS_U32)HVD_RIU_READ_WORD(((u32Reg)+2)<<1)<<16 ) ) 134 135 #define _HVD_ReadRegBit( u32Reg, u8Mask ) (HVD_RIU_READ_BYTE(((u32Reg)<<1) - ((u32Reg) & 1)) & (u8Mask)) 136 137 #define _HVD_ReadWordBit( u32Reg, u16Mask ) (_HVD_Read2Byte( u32Reg ) & (u16Mask)) 138 139 #define _HVD_WriteRegBit( u32Reg, bEnable, u8Mask ) \ 140 HVD_MACRO_START \ 141 HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) | (u8Mask)) : \ 142 (HVD_RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) & ~(u8Mask))); \ 143 HVD_MACRO_END 144 145 #define _HVD_WriteByte( u32Reg, u8Val ) \ 146 HVD_MACRO_START \ 147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \ 148 HVD_MACRO_END 149 150 #define _HVD_Write2Byte( u32Reg, u16Val ) \ 151 HVD_MACRO_START \ 152 if ( ((u32Reg) & 0x01) ) \ 153 { \ 154 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \ 155 HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \ 156 } \ 157 else \ 158 { \ 159 HVD_RIU_WRITE_WORD( ((u32Reg)<<1) , u16Val); \ 160 } \ 161 HVD_MACRO_END 162 163 #define _HVD_Write3Byte( u32Reg, u32Val ) \ 164 if ((u32Reg) & 0x01) \ 165 { \ 166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \ 167 HVD_RIU_WRITE_WORD( (u32Reg + 1)<<1 , ((u32Val) >> 8)); \ 168 } \ 169 else \ 170 { \ 171 HVD_RIU_WRITE_WORD( (u32Reg) << 1, u32Val); \ 172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \ 173 } 174 175 #define _HVD_Write4Byte( u32Reg, u32Val ) \ 176 HVD_MACRO_START \ 177 if ((u32Reg) & 0x01) \ 178 { \ 179 HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \ 180 HVD_RIU_WRITE_WORD( ((u32Reg) + 1)<<1 , ( (u32Val) >> 8)); \ 181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \ 182 } \ 183 else \ 184 { \ 185 HVD_RIU_WRITE_WORD( (u32Reg) <<1 , u32Val); \ 186 HVD_RIU_WRITE_WORD( ((u32Reg) + 2)<<1 , ((u32Val) >> 16)); \ 187 } \ 188 HVD_MACRO_END 189 190 #define _HVD_WriteByteMask( u32Reg, u8Val, u8Msk ) \ 191 HVD_MACRO_START \ 192 HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32Reg) & 1))) & ~(u8Msk)) | ((u8Val) & (u8Msk))); \ 193 HVD_MACRO_END 194 195 #define _HVD_WriteWordMask( u32Reg, u16Val , u16Msk) \ 196 HVD_MACRO_START \ 197 if ( ((u32Reg) & 0x01) ) \ 198 { \ 199 _HVD_WriteByteMask( ((u32Reg)+1) , (((u16Val) & 0xff00)>>8) , (((u16Msk)&0xff00)>>8) ); \ 200 _HVD_WriteByteMask( (u32Reg) , ((u16Val) & 0x00ff) , ((u16Msk)&0x00ff) ); \ 201 } \ 202 else \ 203 { \ 204 HVD_RIU_WRITE_WORD( ((u32Reg)<<1) , (((u16Val) & (u16Msk)) | (_HVD_Read2Byte( u32Reg ) & (~( u16Msk )))) ); \ 205 } \ 206 HVD_MACRO_END 207 208 //------------------------------------------------------------------------------ 209 // MVD Reg 210 //------------------------------------------------------------------------------ 211 #define REG_MVD_BASE (0x1100) 212 213 #define MVD_REG_STAT_CTRL (REG_MVD_BASE) 214 #define MVD_REG_CTRL_RST BIT(0) 215 #define MVD_REG_CTRL_INIT BIT(2) 216 #define MVD_REG_DISCONNECT_MIU BIT(6) 217 218 //------------------------------------------------------------------------------ 219 // HVD Reg 220 //------------------------------------------------------------------------------ 221 #define REG_HVD_BASE (0x1B00) 222 223 #define HVD_REG_REV_ID (REG_HVD_BASE+(( 0x0000)<<1)) 224 #define HVD_REG_RESET (REG_HVD_BASE+(( 0x0001)<<1)) 225 #define HVD_REG_RESET_SWRST BIT(0) 226 #define HVD_REG_RESET_SWRST_FIN BIT(2) 227 #define HVD_REG_RESET_STOP_BBU BIT(3) 228 #define HVD_REG_RESET_MIU_RDY BIT(4) 229 #define HVD_REG_RESET_HK_AVS_MODE BIT(8) 230 #define HVD_REG_RESET_HK_RM_MODE BIT(9) 231 #define HVD_REG_RESET_HK_RV9_DEC_MODE BIT(10) 232 #define HVD_REG_RESET_MIU_128 BIT(11) 233 #define HVD_REG_ESB_ST_ADDR_L (REG_HVD_BASE+(( 0x0002)<<1)) 234 #define HVD_REG_ESB_ST_ADDR_H (REG_HVD_BASE+(( 0x0003)<<1)) 235 // #define HVD_REG_ESB_ST_ADDR_H_MASK 10 236 #define HVD_REG_ESB_LENGTH_L (REG_HVD_BASE+(( 0x0004)<<1)) 237 #define HVD_REG_ESB_LENGTH_H (REG_HVD_BASE+(( 0x0005)<<1)) 238 // #define HVD_REG_ESB_LENGTH_H_BITS 10 239 #define HVD_REG_ESB_RPTR (REG_HVD_BASE+(( 0x0006)<<1)) 240 #define HVD_REG_ESB_RPTR_POLL BIT(0) 241 // #define HVD_REG_ESB_RPTR_L_OFFSET 7 242 // #define HVD_REG_ESB_RPTR_L_BITS 9 243 // #define HVD_REG_ESB_RPTR_L_MASK BMASK( ( HVD_REG_ESB_RPTR_L_BITS+HVD_REG_ESB_RPTR_L_OFFSET ) : HVD_REG_ESB_RPTR_L_OFFSET )//0xFF80 244 #define HVD_REG_ESB_RPTR_H (REG_HVD_BASE+(( 0x0007)<<1)) 245 #define HVD_REG_MIF_BBU (REG_HVD_BASE+(( 0x0008)<<1)) 246 #define HVD_REG_MIF_OFFSET_L_BITS 7 247 #define HVD_REG_MIF_OFFSET_H BIT(12) 248 #define HVD_REG_BBU_TSP_INPUT BIT(8) 249 #define HVD_REG_BBU_PASER_MASK (BIT(10) | BIT(9)) 250 #define HVD_REG_BBU_PASER_DISABLE 0 251 #define HVD_REG_BBU_PASER_ENABLE_ALL BIT(9) 252 #define HVD_REG_BBU_PASER_ENABLE_03 (BIT(9)|BIT(10)) 253 #define HVD_REG_BBU_AUTO_NAL_TAB BIT(11) 254 #define HVD_REG_NAL_TBL_ST_ADDR_L (REG_HVD_BASE+(( 0x0009)<<1)) 255 #define HVD_REG_NAL_TBL_ST_ADDR_H (REG_HVD_BASE+(( 0x000A)<<1)) 256 #define HVD_REG_HI_MBOX0_L (REG_HVD_BASE+(( 0x000B)<<1)) 257 #define HVD_REG_HI_MBOX0_H (REG_HVD_BASE+(( 0x000C)<<1)) 258 #define HVD_REG_HI_MBOX1_L (REG_HVD_BASE+(( 0x000D)<<1)) 259 #define HVD_REG_HI_MBOX1_H (REG_HVD_BASE+(( 0x000E)<<1)) 260 #define HVD_REG_HI_MBOX_SET (REG_HVD_BASE+(( 0x000F)<<1)) 261 #define HVD_REG_HI_MBOX0_SET BIT(0) 262 #define HVD_REG_HI_MBOX1_SET BIT(8) 263 #define HVD_REG_RISC_MBOX_CLR (REG_HVD_BASE+(( 0x0010)<<1)) 264 #define HVD_REG_RISC_MBOX0_CLR BIT(0) 265 #define HVD_REG_RISC_MBOX1_CLR BIT(1) 266 #define HVD_REG_RISC_ISR_CLR BIT(2) 267 #define HVD_REG_NAL_WPTR_SYNC BIT(3) 268 #define HVD_REG_RISC_ISR_MSK BIT(6) 269 #define HVD_REG_RISC_ISR_FORCE BIT(10) 270 #define HVD_REG_RISC_MBOX_RDY (REG_HVD_BASE+(( 0x0011)<<1)) 271 #define HVD_REG_RISC_MBOX0_RDY BIT(0) 272 #define HVD_REG_RISC_MBOX1_RDY BIT(4) 273 #define HVD_REG_RISC_ISR_VALID BIT(8) 274 #define HVD_REG_HI_MBOX_RDY (REG_HVD_BASE+(( 0x0012)<<1)) 275 #define HVD_REG_HI_MBOX0_RDY BIT(0) 276 #define HVD_REG_HI_MBOX1_RDY BIT(8) 277 #define HVD_REG_RISC_MBOX0_L (REG_HVD_BASE+(( 0x0013)<<1)) 278 #define HVD_REG_RISC_MBOX0_H (REG_HVD_BASE+(( 0x0014)<<1)) 279 #define HVD_REG_RISC_MBOX1_L (REG_HVD_BASE+(( 0x0015)<<1)) 280 #define HVD_REG_RISC_MBOX1_H (REG_HVD_BASE+(( 0x0016)<<1)) 281 #define HVD_REG_POLL_NAL_RPTR (REG_HVD_BASE+(( 0x0017)<<1)) 282 #define HVD_REG_POLL_NAL_RPTR_BIT BIT(0) 283 #define HVD_REG_NAL_RPTR_HI (REG_HVD_BASE+(( 0x0018)<<1)) 284 #define HVD_REG_NAL_WPTR_HI (REG_HVD_BASE+(( 0x0019)<<1)) 285 #define HVD_REG_NAL_TAB_LEN (REG_HVD_BASE+(( 0x0020)<<1)) 286 287 #define HVD_REG_DEBUG_DAT_L (REG_HVD_BASE+(( 0x0023)<<1)) 288 #define HVD_REG_DEBUG_DAT_H (REG_HVD_BASE+(( 0x0024)<<1)) 289 #define HVD_REG_DEBUG_SEL (REG_HVD_BASE+(( 0x0025)<<1)) 290 291 292 /* hvd bs2 reg */ 293 #define HVD_REG_ESB_ST_ADDR_L_BS2 (REG_HVD_BASE+(( 0x0032)<<1)) 294 #define HVD_REG_ESB_ST_ADDR_H_BS2 (REG_HVD_BASE+(( 0x0033)<<1)) 295 #define HVD_REG_ESB_LENGTH_L_BS2 (REG_HVD_BASE+(( 0x0034)<<1)) 296 #define HVD_REG_ESB_LENGTH_H_BS2 (REG_HVD_BASE+(( 0x0035)<<1)) 297 #define HVD_REG_ESB_RPTR_BS2 (REG_HVD_BASE+(( 0x0036)<<1)) 298 #define HVD_REG_ESB_RPTR_H_BS2 (REG_HVD_BASE+(( 0x0037)<<1)) 299 #define HVD_REG_MIF_BBU_BS2 (REG_HVD_BASE+(( 0x0038)<<1)) 300 #define HVD_REG_MIF_OFFSET_L_BITS_BS2 7 301 #define HVD_REG_MIF_OFFSET_H_BS2 BIT(12) 302 #define HVD_REG_BBU_TSP_INPUT_BS2 BIT(8) 303 #define HVD_REG_BBU_PASER_MASK_BS2 (BIT(10) | BIT(9)) 304 #define HVD_REG_BBU_PASER_DISABLE_BS2 0 305 #define HVD_REG_BBU_PASER_ENABLE_ALL_BS2 BIT(9) 306 #define HVD_REG_BBU_PASER_ENABLE_03_BS2 (BIT(9)|BIT(10)) 307 #define HVD_REG_BBU_AUTO_NAL_TAB_BS2 BIT(11) 308 #define HVD_REG_NAL_TBL_ST_ADDR_L_BS2 (REG_HVD_BASE+(( 0x0039)<<1)) 309 #define HVD_REG_NAL_TBL_ST_ADDR_H_BS2 (REG_HVD_BASE+(( 0x003A)<<1)) 310 #define HVD_REG_NAL_RPTR_HI_BS2 (REG_HVD_BASE+(( 0x003B)<<1)) 311 #define HVD_REG_NAL_WPTR_HI_BS2 (REG_HVD_BASE+(( 0x003C)<<1)) 312 #define HVD_REG_NAL_TAB_LEN_BS2 (REG_HVD_BASE+(( 0x003D)<<1)) 313 314 //------------------------------------------------------------------------------ 315 // ChipTop Reg 316 //------------------------------------------------------------------------------ 317 318 #define CHIPTOP_REG_BASE (0x1E00 ) 319 #define CLKGEN0_REG_BASE (0x0B00 ) 320 321 #define REG_TOP_PSRAM0_1_MIUMUX (CHIPTOP_REG_BASE+(0x002D<<1)) //TODO 322 #define TOP_CKG_PSRAM0_MASK BMASK(1:0) 323 #define TOP_CKG_PSRAM0_DIS BIT(0) 324 #define TOP_CKG_PSRAM0_INV BIT(1) 325 #define TOP_CKG_PSRAM1_MASK BMASK(3:2) 326 #define TOP_CKG_PSRAM1_DIS BIT(0) 327 #define TOP_CKG_PSRAM1_INV BIT(1) 328 #define TOP_MIU_MUX_G07_MASK BMASK(7:6) 329 #define TOP_MIU_MUX_G07_OD_LSB_R BITS(7:6,0) 330 #define TOP_MIU_MUX_G07_GOP2_R BITS(7:6,1) 331 #define TOP_MIU_MUX_G08_MASK BMASK(9:8) 332 #define TOP_MIU_MUX_G08_OD_LSB_W BITS(9:8,0) 333 #define TOP_MIU_MUX_G08_VE_W BITS(9:8,1) 334 #define TOP_MIU_MUX_G15_MASK BMASK(11:10) 335 #define TOP_MIU_MUX_G15_GOP2_R BITS(11:10,0) 336 #define TOP_MIU_MUX_G15_OD_LSB_R BITS(11:10,1) 337 #define TOP_MIU_MUX_G1A_MASK BMASK(13:12) 338 #define TOP_MIU_MUX_G1A_VE_W BITS(13:12,0) 339 #define TOP_MIU_MUX_G1A_OD_LSB_W BITS(13:12,1) 340 #define TOP_MIU_MUX_G26_MASK BMASK(15:14) 341 #define TOP_MIU_MUX_G26_RVD_RW BITS(15:14,0) 342 #define TOP_MIU_MUX_G26_SVD_INTP_R BITS(15:14,1) 343 #define TOP_MIU_MUX_G26_MVD_R BITS(15:14,2) 344 345 #define REG_TOP_VPU (CLKGEN0_REG_BASE+(0x0030<<1)) 346 #define TOP_CKG_VPU_MASK BMASK(3:0) 347 #define TOP_CKG_VPU_DIS BIT(0) 348 #define TOP_CKG_VPU_INV BIT(1) 349 #define TOP_CKG_VPU_CLK_MASK BMASK(3:2) 350 #define TOP_CKG_VPU_160MHZ BITS(3:2,0) 351 #define TOP_CKG_VPU_144MHZ BITS(3:2,1) 352 #define TOP_CKG_VPU_123MHZ BITS(3:2,2) 353 #define TOP_CKG_VPU_108MHZ BITS(3:2,3) 354 // #define TOP_CKG_VPU_96MHZ BITS(6:2,4) 355 // #define TOP_CKG_VPU_72MHZ BITS(6:2,5) 356 // #define TOP_CKG_VPU_MCU BITS(6:2,8) 357 // #define TOP_CKG_VPU_MIU BITS(6:2,16) 358 // #define TOP_CKG_VPU_XTALI BITS(6:2,24) 359 360 #define REG_TOP_HVD (CLKGEN0_REG_BASE+(0x0031<<1)) 361 #define TOP_CKG_HVD_MASK BMASK(3:0) 362 #define TOP_CKG_HVD_DIS BIT(0) 363 #define TOP_CKG_HVD_INV BIT(1) 364 #define TOP_CKG_HVD_CLK_MASK BMASK(3:2) 365 #define TOP_CKG_HVD_216MHZ BITS(3:2,0) 366 #define TOP_CKG_HVD_172MHZ BITS(3:2,1) 367 #define TOP_CKG_HVD_160MHZ BITS(3:2,2) 368 #define TOP_CKG_HVD_144MHZ BITS(3:2,3) 369 // #define TOP_CKG_HVD_XTAL BITS(5:2,4) 370 // #define TOP_CKG_HVD_MIU BITS(5:2,5) 371 372 373 #define REG_TOP_MVD (CLKGEN0_REG_BASE+(0x0039<<1)) 374 #define TOP_CKG_MVD_MASK BMASK(4:0) 375 #define TOP_CKG_MHVD_DIS BIT(0) 376 #define TOP_CKG_MVD_INV BIT(1) 377 #define TOP_CKG_MVD_CLK_MASK BMASK(4:2) 378 #define TOP_CKG_MVD_216MHZ BITS(4:2,0) 379 #define TOP_CKG_MVD_192MHZ BITS(4:2,1) 380 #define TOP_CKG_MVD_172MHZ BITS(4:2,2) 381 #define TOP_CKG_MVD_144MHZ BITS(4:2,3) 382 #define TOP_CKG_MVD_MIU BITS(4:2,4) 383 #define TOP_CKG_MVD_123MHZ BITS(4:2,5) 384 #define TOP_CKG_MVD_XTAL BITS(4:2,7) 385 386 #define REG_TOP_MVD2 (CLKGEN0_REG_BASE+(0x0039<<1)) 387 #define TOP_CKG_MVD2_MASK BMASK(12:8) 388 #define TOP_CKG_MHVD2_DIS BIT(8) 389 #define TOP_CKG_MVD2_INV BIT(9) 390 #define TOP_CKG_MVD2_CLK_MASK BMASK(12:10) 391 #define TOP_CKG_MVD2_216MHZ BITS(12:10,0) 392 #define TOP_CKG_MVD2_192MHZ BITS(12:10,1) 393 #define TOP_CKG_MVD2_172MHZ BITS(12:10,2) 394 #define TOP_CKG_MVD2_144MHZ BITS(12:10,3) 395 #define TOP_CKG_MVD2_MIU BITS(12:10,4) 396 #define TOP_CKG_MVD2_123MHZ BITS(12:10,5) 397 #define TOP_CKG_MVD2_XTAL BITS(12:10,7) 398 399 #define REG_TOP_HVD_CLK (CLKGEN0_REG_BASE+(0x003F<<1)) 400 #define TOP_CLK_HVD_VP8_MASK BMASK(1:0) 401 #define TOP_CLK_HVD_VP8_DIS BIT(0) 402 #define TOP_CLK_HVD_VP8_INV BIT(1) 403 #define TOP_CLK_MIU_HVD_MASK BMASK(5:4) 404 #define TOP_CLK_MIU_HVD_DIS BIT(0) 405 #define TOP_CLK_MIU_HVD_INV BIT(1) 406 #define TOP_CLK_RM_MIU_HVD_MASK BMASK(9:8) 407 #define TOP_CLK_RM_MIU_HVD_DIS BIT(0) 408 #define TOP_CLK_RM_MIU_HVD_INV BIT(1) 409 #define TOP_CLK_MIU_HVD_VP8_MASK BMASK(13:12) 410 #define TOP_CLK_MIU_HVD_VP8_DIS BIT(0) 411 #define TOP_CLK_MIU_HVD_VP8_INV BIT(1) 412 413 #define REG_TOP_UART_SEL0 (CHIPTOP_REG_BASE+(0x0053<<1)) 414 #define REG_TOP_UART_SEL_0_MASK BMASK(3:0) 415 #define REG_TOP_UART_SEL_MHEG5 BITS(3:0 , 1) 416 #define REG_TOP_UART_SEL_VD_MHEG5 BITS(3:0 , 2) 417 #define REG_TOP_UART_SEL_TSP BITS(3:0 , 3) 418 #define REG_TOP_UART_SEL_PIU_0 BITS(3:0 , 4) 419 #define REG_TOP_UART_SEL_PIU_1 BITS(3:0 , 5) 420 #define REG_TOP_UART_SEL_PIU_FAST BITS(3:0 , 7) 421 #define REG_TOP_UART_SEL_VD_MCU_51_TXD0 BITS(3:0 , 10) 422 #define REG_TOP_UART_SEL_VD_MCU_51_TXD1 BITS(3:0 , 11) 423 //------------------------------------------------------------------------------ 424 // MIU Reg 425 //------------------------------------------------------------------------------ 426 #define MIU0_REG_HVD_BASE (0x1200) 427 #define MIU1_REG_HVD_BASE (0x0600) 428 429 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1)) 430 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1)) 431 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1)) 432 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1)) 433 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1)) 434 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1)) 435 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1)) 436 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1)) 437 438 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1)) 439 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1)) 440 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1)) 441 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1)) 442 #define MIU1_REG_SEL0 (MIU1_REG_HVD_BASE+(( 0x0078)<<1)) 443 444 445 #define MIU_HVD_RW (BIT(10)|BIT(11)) 446 #define MIU_MVD_RW (BIT(5)|BIT(6)) 447 448 //------------------------------------------------------------------------------------------------- 449 // Type and Structure 450 //------------------------------------------------------------------------------------------------- 451 452 453 #endif // _REG_HVD_H_ 454 455