Home
last modified time | relevance | path

Searched refs:REG_CLKGEN2_STC_SRC_SYNTH (Results 1 – 8 of 8) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/
H A DregTSP.h250 #define REG_CLKGEN2_STC_SRC_SYNTH 0x0000 macro
H A DhalTSP.c500 | (REG_CLKGEN2_STC_SRC_SYNTH << (REG_CLKGEN2_STC_SRC_SHIFT+REG_CLKGEN2_STC2_SHIFT)); in HAL_TSP_Power()
503 | (REG_CLKGEN2_STC_SRC_SYNTH << (REG_CLKGEN2_STC_SRC_SHIFT+REG_CLKGEN2_STC3_SHIFT)); in HAL_TSP_Power()
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregTSP.h189 #define REG_CLKGEN2_STC_SRC_SYNTH 0x0000 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregTSP.h190 #define REG_CLKGEN2_STC_SRC_SYNTH 0x0000 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregTSP.h190 #define REG_CLKGEN2_STC_SRC_SYNTH 0x0000 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/
H A DregTSP.h189 #define REG_CLKGEN2_STC_SRC_SYNTH 0x0000 macro
H A DhalTSP.c617 | (REG_CLKGEN2_STC_SRC_SYNTH << (REG_CLKGEN2_STC_SRC_SHIFT+REG_CLKGEN2_STC2_SHIFT)); in HAL_TSP_Power()
620 | (REG_CLKGEN2_STC_SRC_SYNTH << (REG_CLKGEN2_STC_SRC_SHIFT+REG_CLKGEN2_STC3_SHIFT)); in HAL_TSP_Power()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/
H A DregTSP.h190 #define REG_CLKGEN2_STC_SRC_SYNTH 0x0000 macro