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Searched refs:REG_CLKGEN2_STC3_CW_SEL (Results 1 – 12 of 12) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/
H A DregTSP.h230 #define REG_CLKGEN2_STC3_CW_SEL 0x0200 macro
H A DhalTSP.c2287 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~REG_CLKGEN2_STC3_CW_SEL; in HAL_TSP_STC_Init()
2449 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~REG_CLKGEN2_STC3_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DhalTSP.c311 #define REG_CLKGEN2_STC3_CW_SEL 0x0200UL macro
3679 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC3_CW_SEL; in HAL_TSP_SetSTCSynth()
3685 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) |= REG_CLKGEN2_STC3_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DhalTSP.c311 #define REG_CLKGEN2_STC3_CW_SEL 0x0200UL macro
3662 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC3_CW_SEL; in HAL_TSP_SetSTCSynth()
3668 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) |= REG_CLKGEN2_STC3_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DhalTSP.c319 #define REG_CLKGEN2_STC3_CW_SEL 0x0200UL macro
3758 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC3_CW_SEL; in HAL_TSP_SetSTCSynth()
3764 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) |= REG_CLKGEN2_STC3_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DhalTSP.c319 #define REG_CLKGEN2_STC3_CW_SEL 0x0200UL macro
3719 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC3_CW_SEL; in HAL_TSP_SetSTCSynth()
3725 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) |= REG_CLKGEN2_STC3_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregTSP.h169 #define REG_CLKGEN2_STC3_CW_SEL 0x0200 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregTSP.h170 #define REG_CLKGEN2_STC3_CW_SEL 0x0200 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregTSP.h170 #define REG_CLKGEN2_STC3_CW_SEL 0x0200 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/
H A DregTSP.h169 #define REG_CLKGEN2_STC3_CW_SEL 0x0200 macro
H A DhalTSP.c3951 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~REG_CLKGEN2_STC3_CW_SEL; in HAL_TSP_STC_Init()
4069 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~REG_CLKGEN2_STC3_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/
H A DregTSP.h170 #define REG_CLKGEN2_STC3_CW_SEL 0x0200 macro