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Searched refs:REG_CLKGEN2_DC0_STC2_CW_L (Results 1 – 12 of 12) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/
H A DregTSP.h233 #define REG_CLKGEN2_DC0_STC2_CW_L 0x4B macro
H A DhalTSP.c2299 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_L) = 0x0000; in HAL_TSP_STC_Init()
2373 *u32Sync = TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_L); in HAL_TSP_GetSTCSynth()
2439 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_L) = u32Sync & 0xFFFF; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DhalTSP.c313 #define REG_CLKGEN2_DC0_STC2_CW_L 0x31UL macro
3629 … return (TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_L) | TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_H)); in HAL_TSP_GetSTCSynth()
3671 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_L) = (MS_U16)(u32Sync & 0xFFFF); in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DhalTSP.c313 #define REG_CLKGEN2_DC0_STC2_CW_L 0x31UL macro
3612 … return (TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_L) | TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_H)); in HAL_TSP_GetSTCSynth()
3654 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_L) = (MS_U16)(u32Sync & 0xFFFF); in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DhalTSP.c321 #define REG_CLKGEN2_DC0_STC2_CW_L 0x31UL macro
3708 … return (TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_L) | TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_H)); in HAL_TSP_GetSTCSynth()
3750 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_L) = (MS_U16)(u32Sync & 0xFFFF); in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DhalTSP.c321 #define REG_CLKGEN2_DC0_STC2_CW_L 0x31UL macro
3669 … return (TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_L) | TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_H)); in HAL_TSP_GetSTCSynth()
3711 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_L) = (MS_U16)(u32Sync & 0xFFFF); in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregTSP.h172 #define REG_CLKGEN2_DC0_STC2_CW_L 0x4B macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregTSP.h173 #define REG_CLKGEN2_DC0_STC2_CW_L 0x4B macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregTSP.h173 #define REG_CLKGEN2_DC0_STC2_CW_L 0x4B macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/
H A DregTSP.h172 #define REG_CLKGEN2_DC0_STC2_CW_L 0x4B macro
H A DhalTSP.c3959 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_L) = 0x0000; in HAL_TSP_STC_Init()
4013 *u32Sync = TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_L); in HAL_TSP_GetSTCSynth()
4059 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_L) = u32Sync & 0xFFFF; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/
H A DregTSP.h173 #define REG_CLKGEN2_DC0_STC2_CW_L 0x4B macro