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Searched refs:REG_CLKGEN2_DC0_STC2_CW_H (Results 1 – 12 of 12) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/
H A DregTSP.h234 #define REG_CLKGEN2_DC0_STC2_CW_H 0x4C macro
H A DhalTSP.c2300 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_H) = 0x2800; in HAL_TSP_STC_Init()
2374 *u32Sync |= TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_H) << 16 ; in HAL_TSP_GetSTCSynth()
2440 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_H) = u32Sync >> 16; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DhalTSP.c314 #define REG_CLKGEN2_DC0_STC2_CW_H 0x32UL macro
3629 … return (TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_L) | TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_H)); in HAL_TSP_GetSTCSynth()
3672 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_H) = (MS_U16)((u32Sync >> 16UL) & 0xFFFF); in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DhalTSP.c314 #define REG_CLKGEN2_DC0_STC2_CW_H 0x32UL macro
3612 … return (TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_L) | TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_H)); in HAL_TSP_GetSTCSynth()
3655 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_H) = (MS_U16)((u32Sync >> 16UL) & 0xFFFF); in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DhalTSP.c322 #define REG_CLKGEN2_DC0_STC2_CW_H 0x32UL macro
3708 … return (TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_L) | TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_H)); in HAL_TSP_GetSTCSynth()
3751 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_H) = (MS_U16)((u32Sync >> 16UL) & 0xFFFF); in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DhalTSP.c322 #define REG_CLKGEN2_DC0_STC2_CW_H 0x32UL macro
3669 … return (TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_L) | TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_H)); in HAL_TSP_GetSTCSynth()
3712 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_H) = (MS_U16)((u32Sync >> 16UL) & 0xFFFF); in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregTSP.h173 #define REG_CLKGEN2_DC0_STC2_CW_H 0x4C macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregTSP.h174 #define REG_CLKGEN2_DC0_STC2_CW_H 0x4C macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregTSP.h174 #define REG_CLKGEN2_DC0_STC2_CW_H 0x4C macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/
H A DregTSP.h173 #define REG_CLKGEN2_DC0_STC2_CW_H 0x4C macro
H A DhalTSP.c3960 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_H) = 0x2800; in HAL_TSP_STC_Init()
4014 *u32Sync |= TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_H) << 16 ; in HAL_TSP_GetSTCSynth()
4060 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_H) = u32Sync >> 16; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/
H A DregTSP.h174 #define REG_CLKGEN2_DC0_STC2_CW_H 0x4C macro