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Searched refs:REG_CLKGEN2_BASE (Results 1 – 25 of 38) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dmhal_xc_chip_config.h483 #define REG_CLKGEN2_BASE 0x100A00UL macro
771 #define REG_CKG_S2_MECLK (REG_CLKGEN2_BASE + 0x80 )
776 #define REG_CKG_S2_MGCLK (REG_CLKGEN2_BASE + 0x82 )
781 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 )
789 #define REG_CKG_S2_FICLK_F1 (REG_CLKGEN2_BASE + 0xC2 )
796 #define REG_CKG_S2_FICLK_F2 (REG_CLKGEN2_BASE + 0xC3 )
803 #define REG_CKG_S2_FICLK2_F2 (REG_CLKGEN2_BASE + 0xC3 )
824 #define REG_CKG_S2_FODCLK (REG_CLKGEN2_BASE + 0xC4 )
830 #define REG_CKG_S2_ODCLK (REG_CLKGEN2_BASE + 0xC6 )
839 #define REG_CKG_S2_IDCLK0 (REG_CLKGEN2_BASE + 0xC8 ) // off-line detect idclk
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/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_xc_chip_config.h555 #define REG_CLKGEN2_BASE 0x100A00UL macro
657 #define L_CLKGEN2(x) BK_REG_L(REG_CLKGEN2_BASE, x)
658 #define H_CLKGEN2(x) BK_REG_H(REG_CLKGEN2_BASE, x)
931 #define REG_CKG_S2_MECLK (REG_CLKGEN2_BASE + 0x80 )
936 #define REG_CKG_S2_MGCLK (REG_CLKGEN2_BASE + 0x82 )
941 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 )
949 #define REG_CKG_S2_FICLK_F1 (REG_CLKGEN2_BASE + 0xC2 )
956 #define REG_CKG_S2_FICLK_F2 (REG_CLKGEN2_BASE + 0xC3 )
985 #define REG_CKG_S2_FODCLK (REG_CLKGEN2_BASE + 0xC4 )
991 #define REG_CKG_S2_ODCLK (REG_CLKGEN2_BASE + 0xC6 )
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_xc_chip_config.h568 #define REG_CLKGEN2_BASE 0x100A00UL macro
669 #define L_CLKGEN2(x) BK_REG_L(REG_CLKGEN2_BASE, x)
670 #define H_CLKGEN2(x) BK_REG_H(REG_CLKGEN2_BASE, x)
943 #define REG_CKG_S2_MECLK (REG_CLKGEN2_BASE + 0x80 )
948 #define REG_CKG_S2_MGCLK (REG_CLKGEN2_BASE + 0x82 )
953 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 )
961 #define REG_CKG_S2_FICLK_F1 (REG_CLKGEN2_BASE + 0xC2 )
968 #define REG_CKG_S2_FICLK_F2 (REG_CLKGEN2_BASE + 0xC3 )
997 #define REG_CKG_S2_FODCLK (REG_CLKGEN2_BASE + 0xC4 )
1003 #define REG_CKG_S2_ODCLK (REG_CLKGEN2_BASE + 0xC6 )
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_xc_chip_config.h573 #define REG_CLKGEN2_BASE 0x100A00UL macro
674 #define L_CLKGEN2(x) BK_REG_L(REG_CLKGEN2_BASE, x)
675 #define H_CLKGEN2(x) BK_REG_H(REG_CLKGEN2_BASE, x)
948 #define REG_CKG_S2_MECLK (REG_CLKGEN2_BASE + 0x80 )
953 #define REG_CKG_S2_MGCLK (REG_CLKGEN2_BASE + 0x82 )
958 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 )
966 #define REG_CKG_S2_FICLK_F1 (REG_CLKGEN2_BASE + 0xC2 )
973 #define REG_CKG_S2_FICLK_F2 (REG_CLKGEN2_BASE + 0xC3 )
1002 #define REG_CKG_S2_FODCLK (REG_CLKGEN2_BASE + 0xC4 )
1008 #define REG_CKG_S2_ODCLK (REG_CLKGEN2_BASE + 0xC6 )
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_xc_chip_config.h559 #define REG_CLKGEN2_BASE 0x100A00UL macro
661 #define L_CLKGEN2(x) BK_REG_L(REG_CLKGEN2_BASE, x)
662 #define H_CLKGEN2(x) BK_REG_H(REG_CLKGEN2_BASE, x)
935 #define REG_CKG_S2_MECLK (REG_CLKGEN2_BASE + 0x80 )
940 #define REG_CKG_S2_MGCLK (REG_CLKGEN2_BASE + 0x82 )
945 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 )
953 #define REG_CKG_S2_FICLK_F1 (REG_CLKGEN2_BASE + 0xC2 )
960 #define REG_CKG_S2_FICLK_F2 (REG_CLKGEN2_BASE + 0xC3 )
989 #define REG_CKG_S2_FODCLK (REG_CLKGEN2_BASE + 0xC4 )
995 #define REG_CKG_S2_ODCLK (REG_CLKGEN2_BASE + 0xC6 )
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_xc_chip_config.h464 #define REG_CLKGEN2_BASE 0x100A00UL macro
817 #define REG_CKG_S2_MECLK (REG_CLKGEN2_BASE + 0x80 )
822 #define REG_CKG_S2_MGCLK (REG_CLKGEN2_BASE + 0x82 )
827 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 )
835 #define REG_CKG_S2_FICLK_F1 (REG_CLKGEN2_BASE + 0xC2 )
842 #define REG_CKG_S2_FICLK_F2 (REG_CLKGEN2_BASE + 0xC3 )
849 #define REG_CKG_S2_FICLK2_F2 (REG_CLKGEN2_BASE + 0xC3 )
870 #define REG_CKG_S2_FODCLK (REG_CLKGEN2_BASE + 0xC4 )
876 #define REG_CKG_S2_ODCLK (REG_CLKGEN2_BASE + 0xC6 )
885 #define REG_CKG_S2_IDCLK0 (REG_CLKGEN2_BASE + 0xC8 ) // off-line detect idclk
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_xc_chip_config.h523 #define REG_CLKGEN2_BASE 0x100A00UL macro
886 #define REG_CKG_S2_MECLK (REG_CLKGEN2_BASE + 0x80 )
891 #define REG_CKG_S2_MGCLK (REG_CLKGEN2_BASE + 0x82 )
896 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 )
904 #define REG_CKG_S2_FICLK_F1 (REG_CLKGEN2_BASE + 0xC2 )
911 #define REG_CKG_S2_FICLK_F2 (REG_CLKGEN2_BASE + 0xC3 )
940 #define REG_CKG_S2_FODCLK (REG_CLKGEN2_BASE + 0xC4 )
946 #define REG_CKG_S2_ODCLK (REG_CLKGEN2_BASE + 0xC6 )
955 #define REG_CKG_S2_IDCLK0 (REG_CLKGEN2_BASE + 0xC8 ) // off-line detect idclk
973 #define REG_CKG_S2_IDCLK1 (REG_CLKGEN2_BASE + 0xC9 ) // off-line detect idclk
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_xc_chip_config.h510 #define REG_CLKGEN2_BASE 0x100A00UL macro
880 #define REG_CKG_S2_MECLK (REG_CLKGEN2_BASE + 0x80 )
885 #define REG_CKG_S2_MGCLK (REG_CLKGEN2_BASE + 0x82 )
890 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 )
898 #define REG_CKG_S2_FICLK_F1 (REG_CLKGEN2_BASE + 0xC2 )
905 #define REG_CKG_S2_FICLK_F2 (REG_CLKGEN2_BASE + 0xC3 )
934 #define REG_CKG_S2_FODCLK (REG_CLKGEN2_BASE + 0xC4 )
940 #define REG_CKG_S2_ODCLK (REG_CLKGEN2_BASE + 0xC6 )
949 #define REG_CKG_S2_IDCLK0 (REG_CLKGEN2_BASE + 0xC8 ) // off-line detect idclk
967 #define REG_CKG_S2_IDCLK1 (REG_CLKGEN2_BASE + 0xC9 ) // off-line detect idclk
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dmhal_xc_chip_config.h481 #define REG_CLKGEN2_BASE 0x100A00UL macro
771 #define REG_CKG_S2_FICLK_F1 (REG_CLKGEN2_BASE + 0xC2 )
778 #define REG_CKG_S2_FICLK_F2 (REG_CLKGEN2_BASE + 0xC3 )
785 #define REG_CKG_S2_FICLK2_F2 (REG_CLKGEN2_BASE + 0xC3 )
806 #define REG_CKG_S2_FODCLK (REG_CLKGEN2_BASE + 0xC4 )
812 #define REG_CKG_S2_ODCLK (REG_CLKGEN2_BASE + 0xC6 )
821 #define REG_CKG_S2_IDCLK0 (REG_CLKGEN2_BASE + 0xC8 ) // off-line detect idclk
839 #define REG_CKG_S2_IDCLK1 (REG_CLKGEN2_BASE + 0xC9 ) // off-line detect idclk
857 #define REG_CKG_S2_IDCLK2 (REG_CLKGEN2_BASE + 0xCA ) // off-line detect idclk
875 #define REG_CKG_S2_IDCLK3 (REG_CLKGEN2_BASE + 0xD2 ) // off-line detect idclk
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dmhal_xc_chip_config.h584 #define REG_CLKGEN2_BASE 0x100A00 macro
763 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 )
770 #define REG_CKG_S2_MECLK (REG_CLKGEN2_BASE + 0x80 )
775 #define REG_CKG_S2_MGCLK (REG_CLKGEN2_BASE + 0x82 )
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dmhal_xc_chip_config.h590 #define REG_CLKGEN2_BASE 0x100A00 macro
769 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 )
776 #define REG_CKG_S2_MECLK (REG_CLKGEN2_BASE + 0x80 )
781 #define REG_CKG_S2_MGCLK (REG_CLKGEN2_BASE + 0x82 )
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dmhal_xc_chip_config.h590 #define REG_CLKGEN2_BASE 0x100A00 macro
940 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 )
947 #define REG_CKG_S2_MECLK (REG_CLKGEN2_BASE + 0x80 )
952 #define REG_CKG_S2_MGCLK (REG_CLKGEN2_BASE + 0x82 )
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dmhal_xc_chip_config.h592 #define REG_CLKGEN2_BASE 0x100A00 macro
934 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 )
941 #define REG_CKG_S2_MECLK (REG_CLKGEN2_BASE + 0x80 )
946 #define REG_CKG_S2_MGCLK (REG_CLKGEN2_BASE + 0x82 )
H A Dmhal_xc_chip_config.h.0591 #define REG_CLKGEN2_BASE 0x100A00
933 #define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 )
940 #define REG_CKG_S2_MECLK (REG_CLKGEN2_BASE + 0x80 )
945 #define REG_CKG_S2_MGCLK (REG_CLKGEN2_BASE + 0x82 )
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregEMMflt.h137 #define REG_CLKGEN2_BASE (0x100A00<<1) macro
H A DregNDSRASP.h161 #define REG_CLKGEN2_BASE (0x100A00<<1) macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/curry/nsk2/
H A DregEMMflt.h137 #define REG_CLKGEN2_BASE (0x100A00<<1) macro
H A DregNDSRASP.h161 #define REG_CLKGEN2_BASE (0x100A00<<1) macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregEMMflt.h137 #define REG_CLKGEN2_BASE (0x100A00<<1) macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregEMMflt.h137 #define REG_CLKGEN2_BASE (0x100A00<<1) macro
H A DregNDSRASP.h161 #define REG_CLKGEN2_BASE (0x100A00<<1) macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DregEMMflt.h137 #define REG_CLKGEN2_BASE (0x100A00<<1) macro
H A DregNDSRASP.h161 #define REG_CLKGEN2_BASE (0x100A00<<1) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dmhal_xc_chip_config.h388 #define REG_CLKGEN2_BASE 0x100A00 macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dmhal_xc_chip_config.h388 #define REG_CLKGEN2_BASE 0x100A00 macro

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