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MStar hereby reserves the 91// rights to any and all damages, losses, costs and expenses resulting therefrom. 92// 93//////////////////////////////////////////////////////////////////////////////// 94#ifndef MHAL_XC_CONFIG_H 95#define MHAL_XC_CONFIG_H 96 97//------------------------------------------------------------------------------------------------- 98// Chip Configuration 99//------------------------------------------------------------------------------------------------- 100#define MAX_XC_DEVICE_NUM (2) 101#define MAX_XC_DEVICE0_OFFSET (0UL) 102#define MAX_XC_DEVICE1_OFFSET (128UL) 103 104#define MAX_WINDOW_NUM (2) 105#define MAX_FRAME_NUM_IN_MEM (4) // Progressive 106#define MAX_FIELD_NUM_IN_MEM (16) // Interlace 107#define NUM_OF_DIGITAL_DDCRAM (1) 108 109#define SCALER_LINE_BUFFER_MAX (1920UL) 110#define MST_LINE_BFF_MAX MAX(1920, SCALER_LINE_BUFFER_MAX) 111 112#define SUB_MAIN_LINEOFFSET_GUARD_BAND 0 113#define SUB_SCALER_LINE_BUFFER_MAX 960UL - SUB_MAIN_LINEOFFSET_GUARD_BAND 114#define SUB_MST_LINE_BFF_MAX SUB_SCALER_LINE_BUFFER_MAX 115 116#define SC1_SCALER_LINE_BUFFER_MAX (720UL) 117 118#define MS_3D_LINE_BFF_MAX (960UL) 119#define MS_3D_DISPALY_LINE_BFF_MAX (960UL) 120#define PHASE_OFFSET_LIMIT (0x2000UL) 121 122#define XC_BYPASS_DI_SUPPORT TRUE 123 124//hw support fbl 3d or not. if support,can do SBS to LBL and SBS to SBS 125#define HW_3D_SUPPORT_FBL FALSE 126 127// Set DS index max number 128#define DS_MAX_IDX_NUM (15) 129 130// MIU Word (Bytes) 131#define BYTE_PER_WORD (32) // MIU 128: 16Byte/W, MIU 256: 32Byte/W 132#define OFFSET_PIXEL_ALIGNMENT (64) 133#define OPMFETCH_PIXEL_ALIGNMENT (4) 134#define LPLL_LOOPGAIN (16) 135#define LVDS_MPLL_CLOCK_MHZ (432)//(216) 136 137#define FRC_BYTE_PER_WORD 32 138#define MCDI_BYTE_PER_WORD 16 139 140#define DEFAULT_STEP_P 4 //conservative step value 141#define DEFAULT_STEP_I ((DEFAULT_STEP_P*DEFAULT_STEP_P)/2) 142#define STEP_P 2 //recommended step value -> more faster fpll(T3) 143#define STEP_I ((STEP_P*STEP_P)/2) 144#define IPGAIN_REFACTOR 5 145 146// - For HW Bug in PIP when the gap between H-end of sub window and H-end of main window is too small 147#define HW_PIP_BUG_SW_PATCH_FETCH_INCREASE 8 148 149#define F2_WRITE_LIMIT_EN BIT(31) 150#define F2_WRITE_LIMIT_MIN BIT(30) 151 152#define F1_WRITE_LIMIT_EN BIT(31) 153#define F1_WRITE_LIMIT_MIN BIT(30) 154 155#define F2_V_WRITE_LIMIT_EN BIT(15) 156#define F1_V_WRITE_LIMIT_EN BIT(15) 157 158#define F2_OPW_WRITE_LIMIT_EN BIT(31) //for UC 159#define F2_OPW_WRITE_LIMIT_MIN BIT(30) //for UC 160 161#define ADC_MAX_CLK (3500) 162 163#define SUPPORTED_XCDIP_INT 0 //FIXME: DIP Interrupt control are moved to apiXC_DWIN. Related codes should be removed. 164 165#define SUPPORTED_XC_INT ((1UL << SC_INT_VSINT) | \ 166 (1UL << SC_INT_F2_VTT_CHG) | \ 167 (1UL << SC_INT_F1_VTT_CHG) | \ 168 (1UL << SC_INT_F2_VS_LOSE) | \ 169 (1UL << SC_INT_F1_VS_LOSE) | \ 170 (1UL << SC_INT_F2_JITTER) | \ 171 (1UL << SC_INT_F1_JITTER) | \ 172 (1UL << SC_INT_F2_IPVS_SB) | \ 173 (1UL << SC_INT_F1_IPVS_SB) | \ 174 (1UL << SC_INT_F2_IPHCS_DET) | \ 175 (1UL << SC_INT_F1_IPHCS_DET) | \ 176 (1UL << SC_INT_F2_HTT_CHG) | \ 177 (1UL << SC_INT_F1_HTT_CHG) | \ 178 (1UL << SC_INT_F2_HS_LOSE) | \ 179 (1UL << SC_INT_F1_HS_LOSE) | \ 180 (1UL << SC_INT_F2_CSOG) | \ 181 (1UL << SC_INT_F1_CSOG) | \ 182 (1UL << SC_INT_F2_ATP_READY) | \ 183 (1UL << SC_INT_MEMSYNC_MAIN) | \ 184 (1UL << SC_INT_F1_ATP_READY)) 185 186//These table definition is from SC_BK0 spec. 187//Because some chip development is different, it need to check and remap when INT function is used 188#define IRQ_CLEAN_INKERNEL 0 189 190#define IRQ_INT_DIPW 1 191#define IRQ_INT_MEMSYNC_MAIN 3 192#define IRQ_INT_START 4 193#define IRQ_INT_RESERVED1 IRQ_INT_START 194 195#define IRQ_INT_VSINT 5 196#define IRQ_INT_F2_VTT_CHG 6 197#define IRQ_INT_F1_VTT_CHG 7 198#define IRQ_INT_F2_VS_LOSE 8 199#define IRQ_INT_F1_VS_LOSE 9 200#define IRQ_INT_F2_JITTER 10 201#define IRQ_INT_F1_JITTER 11 202#define IRQ_INT_F2_IPVS_SB 12 203#define IRQ_INT_F1_IPVS_SB 13 204#define IRQ_INT_F2_IPHCS_DET 14 205#define IRQ_INT_F1_IPHCS_DET 15 206 207#define IRQ_INT_PWM_RP_L_INT 16 208#define IRQ_INT_PWM_FP_L_INT 17 209#define IRQ_INT_F2_HTT_CHG 18 210#define IRQ_INT_F1_HTT_CHG 19 211#define IRQ_INT_F2_HS_LOSE 20 212#define IRQ_INT_F1_HS_LOSE 21 213#define IRQ_INT_PWM_RP_R_INT 22 214#define IRQ_INT_PWM_FP_R_INT 23 215#define IRQ_INT_F2_CSOG 24 216#define IRQ_INT_F1_CSOG 25 217#define IRQ_INT_F2_RESERVED2 26 218#define IRQ_INT_F1_RESERVED2 27 219#define IRQ_INT_F2_ATP_READY 28 220#define IRQ_INT_F1_ATP_READY 29 221#define IRQ_INT_F2_RESERVED3 30 222#define IRQ_INT_F1_RESERVED3 31 223 224//------------------------------------------------------------------------------------------------- 225// Chip Feature 226//------------------------------------------------------------------------------------------------- 227/* 12 frame mode for progessive */ 228#define _12FRAME_BUFFER_PMODE_SUPPORTED 0 229/* 8 frame mode for progessive */ 230#define _8FRAME_BUFFER_PMODE_SUPPORTED 0 231/* 6 frame mode for progessive */ 232#define _6FRAME_BUFFER_PMODE_SUPPORTED 0 233/* 4 frame mode for progessive */ 234#define _4FRAME_BUFFER_PMODE_SUPPORTED 0 235/* 3 frame mode for progessive */ 236#define _3FRAME_BUFFER_PMODE_SUPPORTED 0 237/* Linear mode */ 238#define _LINEAR_ADDRESS_MODE_SUPPORTED 0 239 240#define SUPPORT_2_FRAME_MIRROR 0 241 242/* 243 Field-packing ( Customized name ) 244 This is a feature in M10. M10 only needs one IPM buffer address. (Other chips need two or three 245 IPM buffer address). We show one of memory format for example at below. 246 247 Block : Y0 C0 L M Y1 C1 248 Each block contain 4 fields (F0 ~ F3) and each fields in one block is 64 bits 249 Y0 has 64 * 4 bits ( 8 pixel for each field ). 250 Y1 has 64 * 4 bits ( 8 pixel for each field ). 251 So, in this memory format, pixel alignment is 16 pixels (OFFSET_PIXEL_ALIGNMENT = 16). 252 For cropping, OPM address offset have to multiple 4. 253*/ 254#define _FIELD_PACKING_MODE_SUPPORTED 1 255 256#if (_FIELD_PACKING_MODE_SUPPORTED) 257 258/* Linear mode */ 259#define _LINEAR_ADDRESS_MODE_SUPPORTED 0 260 261#else 262/* Linear mode */ 263#define _LINEAR_ADDRESS_MODE_SUPPORTED 1 264 265#endif 266 267/* Because fix loop_div, lpll initial set is different between singal port and dual port */ 268#define _FIX_LOOP_DIV_SUPPORTED 0 269 270// You can only enable ENABLE_8_FIELD_SUPPORTED or ENABLE_16_FIELD_SUPPORTED. (one of them) 271// 16 field mode include 8 field configurion in it. ENABLE_8_FIELD_SUPPORTED is specital case in T7 272#define ENABLE_8_FIELD_SUPPORTED 0 273#define ENABLE_16_FIELD_SUPPORTED 1 274#define ENABLE_OPM_WRITE_SUPPORTED 0 275#define ENABLE_YPBPR_PRESCALING_TO_ORIGINAL 0 276#define ENABLE_VD_PRESCALING_TO_DOT75 0 277#define ENABLE_NONSTD_INPUT_MCNR 0 278#define ENABLE_REGISTER_SPREAD 1 279 280#define ENABLE_REQUEST_FBL 1 281#define DELAY_LINE_SC_UP 7 282#define DELAY_LINE_SC_DOWN 8 283 284#define CHANGE_VTT_STEPS 1 285#define CHANGE_VTT_DELAY 0 286 287#define SUPPORT_IMMESWITCH 0 288#define SUPPORT_DVI_AUTO_EQ 1 289#define SUPPORT_MHL 0 // MHL function is done by MHL in utopia not in xc 290#define SUPPORT_SECURITY_MODE 0 291#define SUPPORT_HDMI_RX_NEW_FEATURE 1 292#define SUPPORT_DEVICE1 1 293#define SUPPORT_SEAMLESS_ZAPPING 0 294#define SUPPORT_FRCM_MODE 0 295#define SUPPORT_4K2K_PIP 0 296 297#if defined (MSOS_TYPE_ECOS) 298#define SUPPORT_KERNEL_MLOAD 0 299#else 300#define SUPPORT_KERNEL_MLOAD 1 301#endif 302 303#define SUPPORT_KERNEL_DS 0 304 305#define SUPPORT_OP2_TEST_PATTERN 0 306// Special frame lock means that the frame rates of input and output are the same in HW design spec. 307#define SUPPORT_SPECIAL_FRAMELOCK TRUE 308 309#define LD_ENABLE 0 310 311#define FRC_INSIDE FALSE 312 313// 480p and 576p have FPLL problem in HV mode. 314// So only allow HV mode for 720P 315#define ONLY_ALLOW_HV_MODE_FOR_720P 0// 1 //FIXME: Check this flow 316 317// T12, T13 cannot use IP_HDMI for HV mode 318// We must use IP_HDMI for HV mode, otherwise 480i 576i will have color space proble,m 319//Note: if use IP_HDMI, MApi_XC_GetDEWindow() cannot get value correctly 320// and IP_HDMI is set in MApi_XC_SetInputSource(), so cannot change dynamically 321// Thus, chip could use this flag to determine whether could do HV mode or not. 322#define SUPPORT_IP_HDMI_FOR_HV_MODE 1 323 324// version1: edison: 4k2k@mm :mvop->dip->gop->ursa; 4k2k@hdmi:hdmi->ursa 325// version2: nike: 326// version3: napoli: frc: double frc and width 327// version4: monaco: frcm and 2p 328// version5: clippers: 4k2k@60 MVOP directly output to HVSP 329// version7: Kano: 4K2K input use FBL 330#define HW_DESIGN_4K2K_VER (7) 331 332// version0: Not support TV chip as HDMITx 333// version1: Maserati + Raptor 334// version2: Maxim + inside HDMITx 335#define HW_DESIGN_HDMITX_VER (0) 336 337// version1: Kano: 338// version2: Curry: HDR frome maserati 339#define HW_DESIGN_HDR_VER (2) 340 341#define DISABLE_PIP_FUNCTION 342#define DISABLE_HW_PATTERN_FUNCTION 343#define DISABLE_3D_FUNCTION 344 345#define HW_DESIGN_3D_VER (3) 346#define HW_2DTO3D_SUPPORT FALSE 347#define HW_2DTO3D_VER (4) 348#define HW_2DTO3D_BYTE_PER_WORD (16) 349#define HW_2DTO3D_PATCH FALSE //a1 u01:2d to 3d hw bug 350//HW support check board and pixel alternative 351#define HW_SUPPORT_3D_CB_AND_PA FALSE 352//M10, A2, J2 HW will automatic use IPM fetch's reg setting to alignment IPM fetch, so skip sw alignment 353//and for mirror cbcr swap, need check IPM fetch to decide if need swap 354#define HW_IPM_FETCH_ALIGNMENT TRUE 355//hw support 2 line mode deinterlace for interlace or not 356#define HW_2LINEMODE_DEINTERLACE_SUPPORT FALSE 357#define HW_CLK_CTRL TRUE 358#define MLG_1024 359 360#define OSD_LAYER_NUM (4) 361#define VIDEO_OSD_SWITCH_VER (3) 362#define VIDEO_OSD_SWITCH_BOX 363// type: 0-TV, 1-STB 364#define VIDEO_OSD_SWITCH_TYPE (1) 365 366//#define FA_1920X540_OUTPUT 367//#define TBP_1920X2160_OUTPUT 368#define _ENABLE_SW_DS 0 369#define DS_BUFFER_NUM_EX 6 370#define DS_MAX_INDEX 6 371 372#define ENABLE_64BITS_COMMAND 1 373#define ENABLE_64BITS_SPREAD_MODE 1 374#define IS_SUPPORT_64BITS_COMMAND(bEnable64bitsCmd, u32DeviceID) ((bEnable64bitsCmd == 1) && (u32DeviceID == 0)) 375 376#define ENABLE_DS_4_BASEADDR_MODE 1 // need enable both ENABLE_64BITS_COMMAND and ENABLE_64BITS_SPREAD_MODE first 377 378#define DS_CMD_LEN_64BITS 8 379//------------------------------------------------------------------------------------------------- 380/// enable ENABLE_MLOAD_SAME_REG_COMBINE you can do: 381/// MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK01_01_L, BIT(N), BIT(N)); 382/// MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK01_01_L, BIT(M), BIT(M)); 383/// MApi_XC_MLoad_Fire(); 384//------------------------------------------------------------------------------------------------- 385#define ENABLE_MLOAD_SAME_REG_COMBINE 1 386 387// need to refine later, test the capibility first 388//#define A3_MLG 389#define SUPPORT_OSD_HSLVDS_PATH 0 390#define XC_SUPPORT_4K2K 0 391 392// if H/W support 2p mode to achieve 600M HZ 393#define XC_SUPPORT_2P_MODE TRUE 394 395//device 1 is interlace out 396#define XC_DEVICE1_IS_INTERLACE_OUT 1 397 398//if H/W support force post-Vscalin-down in DS mode 399#define HW_SUPPORT_FORCE_VSP_IN_DS_MODE TRUE 400 401//if H/W support LPLL lock freqence not lock phase mode 402#define HW_SUPPORT_LOCK_FREQ_ONLY_WITHOUT_LOCK_PHASE FALSE 403 404// if H/W support interlace output timing 405#define HW_SUPPORT_INTERLACE_OUTPUT TRUE 406 407// if H/W support 4k2k_60p output timing 408#define HW_SUPPORT_4K2K_60P_OUTPUT TRUE 409 410#define SUPPORT_HDMI20 1 411 412#define LOCK_FREQ_ONLY_WITHOUT_LOCK_PHASE 0 413 414#define HW_4K2K_VIP_PEAKING_LIMITATION 0 415#define HW_SCALING_LIMITATION 0 //NO LIMITATION 416 417#define XC_SUPPORT_FRC_CONVERT 0 418 419// support 3D DS 420#define SUPPORT_3D_DS 0 421 422#define PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB 0 // support pip&pop by multi sc ,such as sc1 support pip&pop 423 424#define H2V2_PIXEL_SHIFT_PATCH_USING_IP_DE_BYPASS_MODE FALSE // Use IP_DE_BYPASS_MODE as patch 425 426#define XC_SUPPORT_CMA TRUE 427 428#define XC_CMA_8MB 0x0800000 429#define XC_CMA_10MB 0x0A00000 430#define XC_CMA_12MB 0x0C00000 431#define XC_CMA_14MB 0x0E00000 432#define XC_CMA_15MB 0x0F00000 433#define XC_CMA_16MB 0x1000000 434#define XC_CMA_18MB 0x1200000 435#define XC_CMA_20MB 0x1400000 436#define XC_CMA_24MB 0x1800000 437#define XC_CMA_30MB 0x1E00000 438#define XC_CMA_32MB 0x2000000 439#define XC_CMA_36MB 0x2400000 440#define XC_CMA_30MB 0x1E00000 441#define XC_CMA_40MB 0x2800000 442#define XC_CMA_48MB 0x3000000 443#define XC_CMA_60MB 0x3C00000 444#define XC_CMA_72MB 0x4800000 445#define XC_CMA_96MB 0x6000000 446 447#define XC_4K2K_WIDTH_MAX 4500 448#define XC_4K2K_WIDTH_MIN 3000 449#define XC_4K2K_HIGH_MAX 2500 450#define XC_4K2K_HIGH_MIN 1900 451 452#define XC_4K1K_WIDTH_MAX 4500 453#define XC_4K1K_WIDTH_MIN 3000 454#define XC_4K1K_HIGH_MAX 1300 455#define XC_4K1K_HIGH_MIN 900 456 457#define XC_4K_HALFK_WIDTH_MAX 4500 // 4K 0.5K 458#define XC_4K_HALFK_WIDTH_MIN 3000 // 4K 0.5K 459#define XC_4K_HALFK_HIGH_MAX 600 // 4K 0.5K 460#define XC_4K_HALFK_HIGH_MIN 500 // 4K 0.5K 461 462#define XC_2K2K_WIDTH_MAX 2300 463#define XC_2K2K_WIDTH_MIN 1500 464#define XC_2K2K_HIGH_MAX 2500 465#define XC_2K2K_HIGH_MIN 1900 466 467#define XC_FHD_WIDTH_MAX 2300 468#define XC_FHD_WIDTH_MIN 1500 469#define XC_FHD_HIGH_MAX 1300 470#define XC_FHD_HIGH_MIN 900 471 472#define XC_FP1080P_H_SIZE 1920 473#define XC_FP1080P_V_SIZE 2205 474 475#define XC_SUPPORT_FRC_CONVERT 0 476//------------------------------------------------------------------------------------------------- 477// Register base 478//------------------------------------------------------------------------------------------------- 479#define BK_REG_L( x, y ) ((x) | (((y) << 1))) 480#define BK_REG_H( x, y ) (((x) | (((y) << 1))) + 1) 481 482 483// PM 484#define REG_DDC_BASE 0x000400 485#define REG_PM_SLP_BASE 0x000E00 486#define REG_PM_ATOP_BASE 0x002200 487#define REG_PM_DTOP_BASE 0x002300 488#define REG_PM_SLEEP_BASE REG_PM_SLP_BASE//0x0E00//alex_tung 489#define REG_PAD_SAR_BASE 0x001400UL 490#define REG_SCDC0_BASE 0x010700UL 491#define REG_SCDC1_BASE REG_SCDC0_BASE 492#define REG_SCDC2_BASE REG_SCDC0_BASE 493#define REG_SCDC3_BASE REG_SCDC0_BASE 494#define REG_PM_TOP_BASE 0x001E00UL 495#define REG_MHL_CBUS_BANK 0x001F00UL 496#define REG_EFUSE_BASE 0x002000UL 497#define REG_PM_MHL_CBUS_BANK 0x002F00UL 498 499 500//NONPM 501#define REG_MIU0_BASE 0x101200 502#define REG_MIU0_EX_BASE 0x161500 503#define REG_MIU1_BASE 0x100600 504#define REG_MIU2_BASE 0x162000UL 505#define REG_MIU1_EX_BASE 0x162200 506 507#define REG_CHIP_BASE 0x101E00UL 508#define REG_CHIPTOP_BASE 0x100B00 // 0x1E00 - 0x1EFF 509#define REG_UHC0_BASE 0x102400 510#define REG_UHC1_BASE 0x100D00 511#define REG_ADC_ATOP_BASE 0x102500 // 0x2500 - 0x25FF 512#define REG_ADC_DTOP_BASE 0x102600 // 0x2600 - 0x26EF 513#define REG_HDMI_BASE 0x102700 // 0x2700 - 0x27FF 514#define REG_HDMI2_BASE 0x101A00UL 515#define REG_IPMUX_BASE 0x102E00UL 516#define REG_MVOP_BASE 0x101400UL 517#define REG_SUBMVOP_BASE 0x103D00UL 518#if ENABLE_REGISTER_SPREAD 519#define REG_SCALER_BASE 0x130000UL 520#else 521#define REG_SCALER_BASE 0x102F00UL 522#endif 523#define REG_LPLL_BASE 0x103100UL 524#define REG_MOD_BASE 0x103200UL 525#define REG_PWM_BASE 0x13F400UL 526#define REG_MOD_A_BASE 0x111E00UL 527#define REG_AFEC_BASE 0x103500UL 528#define REG_COMB_BASE 0x103600UL 529 530#define REG_HDCPKEY_BASE 0x172500UL 531#define REG_DVI_ATOP_BASE 0x110900UL 532#define REG_DVI_DTOP_BASE 0x110A00UL 533#define REG_DVI_EQ_BASE 0x110A80UL // EQ started from 0x80 534#define REG_HDCP_BASE 0x110AC0UL // HDCP started from 0xC0 535#define REG_ADC_DTOPB_BASE 0x111200UL // ADC DTOPB 536#define REG_DVI_ATOP1_BASE 0x113200UL 537#define REG_DVI_DTOP1_BASE 0x113300UL 538#define REG_DVI_EQ1_BASE 0x113380UL // EQ started from 0x80 539#define REG_HDCP1_BASE 0x1133C0UL // HDCP started from 0xC0 540#define REG_DVI_ATOP2_BASE 0x113400UL 541#define REG_DVI_ATOP3_BASE 0x162F00UL 542#define REG_DVI_DTOP2_BASE 0x113500UL 543#define REG_DVI_EQ2_BASE 0x113580UL // EQ started from 0x80 544#define REG_HDCP2_BASE 0x1135C0UL // HDCP started from 0xC0 545#define REG_DVI_PS_BASE 0x113600UL // DVI power saving 546#define REG_DVI_PS1_BASE 0x113640UL // DVI power saving1 547#define REG_DVI_PS2_BASE 0x113680UL // DVI power saving2 548#define REG_DVI_PS3_BASE 0x1136C0UL // DVI power saving3 549#define REG_DVI_DTOP3_BASE 0x113700UL 550#define REG_DVI_EQ3_BASE 0x113780UL // EQ started from 0x80 551#define REG_HDCP3_BASE 0x1137C0UL // HDCP started from 0xC0 552 553#define REG_VMARK0_BASE 0x173200UL 554#define REG_VMARK1_BASE 0x173300UL 555 556#define REG_CHIP_ID_MAJOR 0x1ECC 557#define REG_CHIP_ID_MINOR 0x1ECD 558#define REG_CHIP_VERSION 0x1ECE 559#define REG_CHIP_REVISION 0x1ECF 560#define REG_CHIP_GPIO1_BASE 0x110300UL 561 562#define REG_COMBO_PHY0_P0_BASE 0x172800UL 563#define REG_COMBO_PHY1_P0_BASE 0x172900UL 564#define REG_COMBO_PHY0_P1_BASE REG_COMBO_PHY0_P0_BASE 565#define REG_COMBO_PHY1_P1_BASE REG_COMBO_PHY1_P0_BASE 566#define REG_COMBO_PHY0_P2_BASE REG_COMBO_PHY0_P0_BASE 567#define REG_COMBO_PHY1_P2_BASE REG_COMBO_PHY1_P0_BASE 568#define REG_COMBO_PHY0_P3_BASE REG_COMBO_PHY0_P0_BASE 569#define REG_COMBO_PHY1_P3_BASE REG_COMBO_PHY1_P0_BASE 570 571#define REG_DVI_DTOP_DUAL_P0_BASE 0x172000UL 572#define REG_DVI_RSV_DUAL_P0_BASE 0x172100UL 573#define REG_HDCP_DUAL_P0_BASE 0x172200UL 574#define REG_DVI_DTOP_DUAL_P1_BASE REG_DVI_DTOP_DUAL_P0_BASE 575#define REG_DVI_RSV_DUAL_P1_BASE REG_DVI_RSV_DUAL_P0_BASE 576#define REG_HDCP_DUAL_P1_BASE REG_HDCP_DUAL_P0_BASE 577#define REG_DVI_DTOP_DUAL_P2_BASE REG_DVI_DTOP_DUAL_P0_BASE 578#define REG_DVI_RSV_DUAL_P2_BASE REG_DVI_RSV_DUAL_P0_BASE 579#define REG_HDCP_DUAL_P2_BASE REG_HDCP_DUAL_P0_BASE 580#define REG_DVI_DTOP_DUAL_P3_BASE REG_DVI_DTOP_DUAL_P0_BASE 581#define REG_DVI_RSV_DUAL_P3_BASE REG_DVI_RSV_DUAL_P0_BASE 582#define REG_HDCP_DUAL_P3_BASE REG_HDCP_DUAL_P0_BASE 583 584#define REG_HDMI_DUAL_0_BASE 0x172300UL 585#define REG_HDMI2_DUAL_0_BASE 0x172400UL 586#define REG_HDMI3_DUAL_0_BASE 0x173400UL 587 588#define REG_COMBO_GP_TOP_BASE 0x172600UL 589#define REG_SECURE_TZPC_BASE 0x172700UL 590 591#define REG_CLKGEN2_BASE 0x100A00 592#define REG_CLKGEN0_BASE 0x100B00 593#define REG_CLKGEN1_BASE 0x103300 594 595#define REG_GOP_BASE 0x120200UL 596 597///URSA Area 598#define REG_FRC_BANK_BASE (0x300000) 599 600#define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x) 601#define H_CLKGEN0(x) BK_REG_H(REG_CLKGEN0_BASE, x) 602#define L_CLKGEN1(x) BK_REG_L(REG_CLKGEN1_BASE, x) 603#define H_CLKGEN1(x) BK_REG_H(REG_CLKGEN1_BASE, x) 604 605 606 607// store bank 608#define LPLL_BK_STORE 609 610// restore bank 611#define LPLL_BK_RESTORE 612 613// switch bank 614#define LPLL_BK_SWITCH(_x_) 615 616//MVOP control 617#define REG_MVOP_HSK (REG_MVOP_BASE + 0x7C) 618#define REG_SUBMVOP_HSK (REG_SUBMVOP_BASE + 0x7C) 619#define REG_MVOP_CROP_H_START (REG_MVOP_BASE + 0x80) 620#define REG_MVOP_CROP_V_START (REG_MVOP_BASE + 0x82) 621#define REG_MVOP_CROP_H_SIZE (REG_MVOP_BASE + 0x84) 622#define REG_MVOP_CROP_V_SIZE (REG_MVOP_BASE + 0x86) 623 624 625//------------------------------------------------------------------------------ 626// Register configure 627//------------------------------------------------------------------------------ 628#define REG_CKG_DACA2 (REG_CHIPTOP_BASE + 0x4C ) //DAC out 629 #define CKG_DACA2_GATED BIT(0) 630 #define CKG_DACA2_INVERT BIT(1) 631 #define CKG_DACA2_MASK BMASK(3:2) 632 #define CKG_DACA2_VIF_CLK (0 << 2) 633 #define CKG_DACA2_VD_CLK (1 << 2) 634 #define CKG_DACA2_EXT_TEST_CLK (2 << 2) 635 #define CKG_DACA2_XTAL (3 << 2) 636 637#define REG_CKG_DACB2 (REG_CHIPTOP_BASE + 0x4D ) //DAC out 638 #define CKG_DACB2_GATED BIT(0) 639 #define CKG_DACB2_INVERT BIT(1) 640 #define CKG_DACB2_MASK BMASK(3:2) 641 #define CKG_DACB2_VIF_CLK (0 << 2) 642 #define CKG_DACB2_VD_CLK (1 << 2) 643 #define CKG_DACB2_EXT_TEST_CLK (2 << 2) 644 #define CKG_DACB2_XTAL (3 << 2) 645 646#define REG_CKG_FMCLK (REG_CHIPTOP_BASE + 0xBB ) 647 #define CKG_FMCLK_GATED BIT(0) 648 #define CKG_FMCLK_INVERT BIT(1) 649 #define CKG_FMCLK_MASK BMASK(3:2) 650 #define CKG_FMCLK_FCLK (0 << 2) 651 #define CKG_FMCLK_MIU_256 (1 << 2) 652 #define CKG_FMCLK_MIU_128 (2 << 2) 653 654#define REG_CKG_SC_ROT (REG_CHIPTOP_BASE + 0xFF ) 655 #define CKG_SC_ROT_GATED BIT(0) 656 #define CKG_SC_ROT_INVERT BIT(1) 657 #define CKG_SC_ROT_MASK BMASK(3:2) 658 #define CKG_SC_ROT_MIU_256 (0 << 2) 659 #define CKG_SC_ROT_MIU_128 (1 << 2) 660 661#define REG_CKG_FICLK_F1 (REG_CHIPTOP_BASE + 0xA2 ) // scaling line buffer, set to fclk if post scaling, set to idclk is pre-scaling 662 #define CKG_FICLK_F1_GATED BIT(0) 663 #define CKG_FICLK_F1_INVERT BIT(1) 664 #define CKG_FICLK_F1_MASK BMASK(3:2) 665 #define CKG_FICLK_F1_IDCLK1 (0 << 2) 666 #define CKG_FICLK_F1_FCLK (1 << 2) 667 668#define REG_CKG_FICLK_F2 (REG_CHIPTOP_BASE + 0xA3 ) // scaling line buffer, set to fclk if post scaling, set to idclk is pre-scaling 669 #define CKG_FICLK_F2_GATED BIT(0) 670 #define CKG_FICLK_F2_INVERT BIT(1) 671 #define CKG_FICLK_F2_MASK BMASK(3:2) 672 #define CKG_FICLK_F2_IDCLK2 (0 << 2) 673 #define CKG_FICLK_F2_FLK (1 << 2) 674 675#define REG_CKG_FICLK2_F2 (REG_CHIPTOP_BASE + 0xA3 ) // scaling line buffer, set to fclk if post scaling, set to idclk is pre-scaling 676 #define CKG_FICLK2_F2_GATED BIT(4) 677 #define CKG_FICLK2_F2_INVERT BIT(5) 678 #define CKG_FICLK2_F2_MASK BMASK(7:6) 679 #define CKG_FICLK2_F2_IDCLK2 (0 << 6) 680 #define CKG_FICLK2_F2_FCLK (1 << 6) 681 682#define REG_CKG_FCLK (REG_CHIPTOP_BASE + 0xA5 ) // after memory, before fodclk 683 #define CKG_FCLK_GATED BIT(0) 684 #define CKG_FCLK_INVERT BIT(1) 685 #define CKG_FCLK_MASK BMASK(5:2) 686 #define CKG_FCLK_170MHZ (0 << 2) //This is 172M, but driver layer use 170M, to compatiable naming 170M 687 #define CKG_FCLK_144MHZ (1 << 2) 688 #define CKG_FCLK_108MHZ (2 << 2) 689 #define CKG_FCLK_86MHZ (3 << 2) 690 #define CKG_FCLK_DEFAULT CKG_FCLK_170MHZ 691 692#define REG_CKG_EDCLK (REG_CHIPTOP_BASE + 0xB7 ) // after memory, before fodclk 693 #define CKG_EDCLK_GATED BIT(0) 694 #define CKG_EDCLK_INVERT BIT(1) 695 #define CKG_EDCLK_MASK BMASK(5:2) 696 #define CKG_EDCLK_170MHZ (0 << 2) //This is 172M, but driver layer use 170M, to compatiable naming 170M 697 #define CKG_EDCLK_144MHZ (1 << 2) 698 #define CKG_EDCLK_108MHZ (2 << 2) 699 #define CKG_EDCLK_86MHZ (3 << 2) 700 #define CKG_EDCLK_DEFAULT CKG_EDCLK_170MHZ 701 702 703#define REG_CKG_ODCLK (REG_CHIPTOP_BASE + 0xA6 ) // output dot clock 704 #define CKG_ODCLK_GATED BIT(0) 705 #define CKG_ODCLK_INVERT BIT(1) 706 #define CKG_ODCLK_MASK BMASK(3:2) 707 #define CKG_ODCLK_CLK_OUT_PIX (0 << 2) 708 709//No use in Kano 710#define REG_CKG_ODCLK_DIV (REG_CHIPTOP_BASE + 0xA7 ) 711 #define CKG_ODCLK_DIV_BY_1 BIT(0) 712 #define CKG_ODCLK_DIV_BY_2 BIT(1) 713 714//No use in Kano 715#define REG_CKG_IDCLK0 (REG_CHIPTOP_BASE + 0xA8 ) // off-line detect idclk 716 #define CKG_IDCLK0_GATED BIT(0) 717 #define CKG_IDCLK0_INVERT BIT(1) 718 #define CKG_IDCLK0_MASK BMASK(4:2) 719 #define CKG_IDCLK0_CLK_ADC (0 << 2) 720 #define CKG_IDCLK0_CLK_DVI (1 << 2) 721 #define CKG_IDCLK0_CLK_VD (2 << 2) 722 #define CKG_IDCLK0_CLK_DC0 (3 << 2) 723 #define CKG_IDCLK0_ODCLK (4 << 2) 724 #define CKG_IDCLK0_XTAL (5 << 2) 725 #define CKG_IDCLK0_CLK_VD_ADC (6 << 2) 726 #define CKG_IDCLK0_CLK_DC1 (7 << 2) 727 728#define REG_CKG_DIP_FCLK (REG_CHIPTOP_BASE + (0x54<<1) +1 ) 729 #define CKG_DIP_FCLK_GATED BIT(0) 730 #define CKG_DIP_FCLK_INVERT BIT(1) 731 #define CKG_DIP_FCLK_MASK BMASK(5:2) 732 #define CKG_DIP_FCLK_172MHZ (0 << 2) 733 #define CKG_DIP_FCLK_144MHZ (1 << 2) 734 #define CKG_DIP_FCLK_108MHZ (2 << 2) 735 #define CKG_DIP_FCLK_192MHZ (3 << 2) 736 737#define REG_CKG_IDCLK1 (REG_CHIPTOP_BASE + 0xAA ) // sub window idclk 738 #define CKG_IDCLK1_GATED BIT(0) 739 #define CKG_IDCLK1_INVERT BIT(1) 740 #define CKG_IDCLK1_MASK BMASK(5:2) 741 #define CKG_IDCLK1_CLK_ADC (0 << 2) 742 #define CKG_IDCLK1_CLK_DVI (1 << 2) 743 #define CKG_IDCLK1_CLK_VD (2 << 2) 744 #define CKG_IDCLK1_CLK_DC0 (3 << 2) 745 #define CKG_IDCLK1_ODCLK (4 << 2) 746 #define CKG_IDCLK1_XTAL (5 << 2) 747 #define CKG_IDCLK1_CLK_VD_ADC (6 << 2) 748 #define CKG_IDCLK1_CLK_DC1 (7 << 2) 749 750//No use in Kano 751#define REG_CKG_PRE_IDCLK1 (REG_CHIPTOP_BASE + 0xBC ) // pre-main window idclk 752 #define CKG_PRE_IDCLK1_MASK BMASK(5:3) 753 #define CKG_PRE_IDCLK1_CLK_ADC (0 << 3) 754 #define CKG_PRE_IDCLK1_CLK_DVI (1 << 3) 755 #define CKG_PRE_IDCLK1_CLK_MHL (2 << 3) 756 757#define REG_CKG_IDCLK2 (REG_CHIPTOP_BASE + 0xAB ) // main window idclk 758 #define CKG_IDCLK2_GATED BIT(0) 759 #define CKG_IDCLK2_INVERT BIT(1) 760 #define CKG_IDCLK2_MASK BMASK(5:2) 761 #define CKG_IDCLK2_CLK_ADC (0 << 2) 762 #define CKG_IDCLK2_CLK_DVI (1 << 2) 763 #define CKG_IDCLK2_CLK_VD (2 << 2) 764 #define CKG_IDCLK2_CLK_DC0 (3 << 2) 765 #define CKG_IDCLK2_ODCLK (4 << 2) 766 #define CKG_IDCLK2_XTAL (5 << 2) 767 #define CKG_IDCLK2_CLK_VD_ADC (6 << 2) 768 #define CKG_IDCLK2_CLK_DC1 (7 << 2) 769 770#define REG_IPMUX_HDR REG_IPMUX_03_H 771#define REG_CLK_HDR (REG_CHIPTOP_BASE + 0x16) 772 773//No use in Kano 774#define REG_CKG_PRE_IDCLK2 (REG_CHIPTOP_BASE + 0xBC ) // pre-main window idclk 775 #define CKG_PRE_IDCLK2_MASK BMASK(8:6) 776 #define CKG_PRE_IDCLK2_CLK_ADC (0 << 6) 777 #define CKG_PRE_IDCLK2_CLK_DVI (1 << 6) 778 #define CKG_PRE_IDCLK2_CLK_MHL (2 << 6) 779 780#define REG_CKG_IDCLK3 (REG_CHIPTOP_BASE + (0x56<<1) ) // sc dip top clk 781 #define CKG_IDCLK3_GATED BIT(0) 782 #define CKG_IDCLK3_INVERT BIT(1) 783 #define CKG_IDCLK3_MASK BMASK(5:2) 784 #define CKG_IDCLK3_CLK_ADC (0 << 2) 785 #define CKG_IDCLK3_CLK_DVI (1 << 2) 786 #define CKG_IDCLK3_CLK_VD (2 << 2) 787 #define CKG_IDCLK3_CLK_DC0 (3 << 2) 788 #define CKG_IDCLK3_ODCLK (4 << 2) 789 #define CKG_IDCLK3_XTAL (10 << 2) 790 #define CKG_IDCLK3_CLK_VD_ADC (6 << 2) 791 #define CKG_IDCLK3_00 (7 << 2) // same as 5 --> also is 0 792 #define CKG_IDCLK3_CLK_DC1 (8 << 2) 793 794#define REG_CKG_PRE_IDCLK3 (REG_CHIPTOP_BASE + 0xBC ) 795 #define CKG_PRE_IDCLK3_MASK BMASK(11:9) 796 #define CKG_PRE_IDCLK3_CLK_ADC (0 << 9) 797 #define CKG_PRE_IDCLK3_CLK_DVI (1 << 9) 798 #define CKG_PRE_IDCLK3_CLK_MHL (2 << 9) 799 800#define REG_CKG_SC1_FCLK (REG_CHIPTOP_BASE + 0xBB ) // SC1 fclk, after memory, before fodclk 801 #define CKG_SC1_FCLK_GATED BIT(4) 802 #define CKG_SC1_FCLK_INVERT BIT(5) 803 #define CKG_SC1_FCLK_MASK BMASK(7:6) 804 #define CKG_SC1_FCLK_172MHZ (0 << 6) 805 #define CKG_SC1_FCLK_144MHZ (1 << 6) 806 #define CKG_SC1_FCLK_108MHZ (2 << 6) 807 #define CKG_SC1_FCLK_86MHZ (3 << 6) 808 809#if 0 810#define REG_CKG_SC1_FECLK_F2 (REG_CHIPTOP_BASE + 0xD8 ) // SC1 feclk, scaling line buffer, set to fclk if post scaling, set to edclk is pre-scaling 811 #define CKG_SC1_FECLK_F2_GATED BIT(0) 812 #define CKG_SC1_FECLK_F2_INVERT BIT(1) 813 #define CKG_SC1_FECLK_F2_MASK BMASK(3:2) 814 #define CKG_SC1_FECLK_F2_SC1_EDCLK (0 << 2) 815 #define CKG_SC1_FECLK_F2_SC1_FCLK (1 << 2) 816 817#define REG_CKG_SC1_FECLK2_F2 (REG_CHIPTOP_BASE + 0xD8 ) // SC1 feclk2, scaling line buffer, set to fclk if post scaling, set to edclk is pre-scaling 818 #define CKG_SC1_FECLK2_F2_GATED BIT(4) 819 #define CKG_SC1_FECLK2_F2_INVERT BIT(5) 820 #define CKG_SC1_FECLK2_F2_MASK BMASK(7:6) 821 #define CKG_SC1_FECLK2_F2_SC1_EDCLK (0 << 6) 822 #define CKG_SC1_FECLK2_F2_SC1_FCLK (1 << 6) 823#endif 824 825#define REG_CKG_SC1_ODCLK (REG_CHIPTOP_BASE + 0xBD ) // SC1 output dot clock 826 #define CKG_SC1_ODCLK_GATED BIT(0) 827 #define CKG_SC1_ODCLK_INVERT BIT(1) 828 #define CKG_SC1_ODCLK_MASK BMASK(3:2) 829 #define CKG_SC1_ODCLK_13M (0 << 2) 830 #define CKG_SC1_ODCLK_EDCLK (1 << 2) 831 832//No use in Kano 833#define REG_CKG_SC1_IDCLK0 (REG_CHIPTOP_BASE + 0xB8 ) // SC1 off-line detect idclk 834 #define CKG_SC1_IDCLK0_GATED BIT(0) 835 #define CKG_SC1_IDCLK0_INVERT BIT(1) 836 #define CKG_SC1_IDCLK0_MASK BMASK(4:2) 837 #define CKG_SC1_IDCLK0_CLK_DVI (1 << 2) 838 #define CKG_SC1_IDCLK0_CLK_DC0 (3 << 2) 839 #define CKG_SC1_IDCLK0_SC1_ODCLK (4 << 2) 840 #define CKG_SC1_IDCLK0_CLK_EXTDI (5 << 2) 841 #define CKG_SC1_IDCLK0_CLK_DC1 (7 << 2) 842 #define CKG_SC1_IDCLK0_XTAL (8 << 2) 843 844//No use in Kano 845#define REG_CKG_SC1_SIDCLK0 (REG_CHIPTOP_BASE + 0xBA ) // SC1 off-line detect sidclk 846 #define CKG_SC1_SIDCLK0_GATED BIT(0) 847 #define CKG_SC1_SIDCLK0_INVERT BIT(1) 848 #define CKG_SC1_SIDCLK0_MASK BMASK(3:2) 849 #define CKG_SC1_SIDCLK0_CLK_DVI (1 << 2) 850 #define CKG_SC1_SIDCLK0_XTAL (3 << 2) 851 852#define REG_CKG_SC1_IDCLK2 (REG_CHIPTOP_BASE + 0xB9 ) // SC1 main window idclk 853 #define CKG_SC1_IDCLK2_GATED BIT(0) 854 #define CKG_SC1_IDCLK2_INVERT BIT(1) 855 #define CKG_SC1_IDCLK2_MASK BMASK(5:2) 856 #define CKG_SC1_IDCLK2_CLK_PRE_H2V2 (0 << 2) 857 #define CKG_SC1_IDCLK2_CLK_DVI (1 << 2) 858 #define CKG_SC1_IDCLK2_ODCLK (2 << 2) 859 #define CKG_SC1_IDCLK2_CLK_DC0 (3 << 2) 860 #define CKG_SC1_IDCLK2_CLK_DC1 (8 << 2) 861 #define CKG_SC1_IDCLK2_XTAL CKG_SC1_IDCLK2_ODCLK // no XTAL, select as OD 862 863#define REG_CKG_SC1_SIDCLK2 (REG_CHIPTOP_BASE + 0xBC ) // SC1 main window sidclk 864 #define CKG_SC1_SIDCLK2_GATED BIT(0) 865 #define CKG_SC1_SIDCLK2_INVERT BIT(1) 866 #define CKG_SC1_SIDCLK2_MASK BMASK(4:2) 867 #define CKG_SC1_SIDCLK2_CLK_DVI (0 << 2) 868 #define CKG_SC1_SIDCLK2_CLK_DC0 (1 << 2) 869 #define CKG_SC1_SIDCLK2_CLK_DC1 (2 << 2) 870 #define CKG_SC1_SIDCLK2_CLK_H2V2 (3 << 2) 871 #define CKG_SC1_SIDCLK2_ODCLK (4 << 2) 872 #define CKG_SC1_SIDCLK2_XTAL (5 << 2) 873 874#define REG_CKG_SC1_EDCLK (REG_CHIPTOP_BASE + 0xBB ) // SC1 main window edclk 875 #define CKG_SC1_EDCLK_GATED BIT(0) 876 #define CKG_SC1_EDCLK_INVERT BIT(1) 877 #define CKG_SC1_EDCLK_MASK BMASK(3:2) 878 #define CKG_SC1_EDCLK_172MHZ (0 << 2) 879 #define CKG_SC1_EDCLK_144MHZ (1 << 2) 880 #define CKG_SC1_EDCLK_108MHZ (2 << 2) 881 #define CKG_SC1_EDCLK_86MHZ (3 << 2) 882 883#define REG_CKG_PDW0 (REG_CHIPTOP_BASE + (0x5B<<1) ) 884 #define CKG_PDW0_GATED BIT(0) 885 #define CKG_PDW0_INVERT BIT(1) 886 #define CKG_PDW0_MASK BMASK(5:2) 887 #define CKG_PDW0_IDCLK2 (0 << 2) 888 #define CKG_PDW0_ODCLK (7 << 2) 889 #define CKG_PDW0_CLK_DC0 (3 << 2) 890 #define CKG_PDW0_CLK_SUB_DC (8 << 2) 891 #define CKG_PDW0_IDCLK1 (4 << 2) 892 #define CKG_PDW0_ODCLK2 (5 << 2) 893 #define CKG_PDW0_IDCLK3_XTAL (10 << 2) 894 895#define REG_CKG_PDW1 (REG_CHIPTOP_BASE + 0xBF ) 896 #define CKG_PDW1_GATED BIT(0) 897 #define CKG_PDW1_INVERT BIT(1) 898 #define CKG_PDW1_MASK BMASK(5:2) 899 #define CKG_PDW1_IDCLK2 (0 << 2) 900 #define CKG_PDW1_ODCLK (1 << 2) 901 #define CKG_PDW1_CLK_DC0 (2 << 2) 902 #define CKG_PDW1_CLK_SUB_DC (3 << 2) 903 #define CKG_PDW1_IDCLK1 (4 << 2) 904 #define CKG_PDW1_ODCLK2 (5 << 2) 905 906#define REG_CKG_OSDC (REG_CHIPTOP_BASE + 0xAB ) 907 #define CKG_OSDC_GATED BIT(0) 908 #define CKG_OSDC_INVERT BIT(1) 909 #define CKG_OSDC_MASK BMASK(3:2) 910 #define CKG_OSDC_CLK_LPLL_OSD (0 << 2) 911 912//#define REG_DE_ONLY_F3 (REG_CHIPTOP_BASE + 0xA0 ) 913 //#define DE_ONLY_F3_MASK BIT(3) 914 915#define REG_DE_ONLY_F2 (REG_CHIPTOP_BASE + 0xB7 ) 916 #define DE_ONLY_F2_MASK BIT(7) 917 918#define REG_DE_ONLY_F1 (REG_CHIPTOP_BASE + 0xB7 ) 919 #define DE_ONLY_F1_MASK BIT(6) 920 921//#define REG_DE_ONLY_F0 (REG_CHIPTOP_BASE + 0xA0 ) 922 //#define DE_ONLY_F0_MASK BIT(0) 923 924 925#define REG_PM_DVI_SRC_CLK (REG_PM_SLP_BASE + 0x96) 926#define REG_PM_DDC_CLK (REG_PM_SLP_BASE + 0x42) 927 928#define REG_CLKGEN0_50_L (REG_CHIPTOP_BASE + 0xA0) 929#define REG_CLKGEN0_51_L (REG_CHIPTOP_BASE + 0xA2) 930 931#define REG_MVOP_MIRROR (REG_MVOP_BASE + 0x76) 932 933#define REG_CKG_S2_GOP_HDR (REG_CLKGEN2_BASE + 0x84 ) 934#define CKG_S2_GOP_HDR_GATED BIT(0) 935#define CKG_S2_GOP_HDR_INVERT BIT(1) 936#define CKG_S2_GOP_HDR_MASK BMASK(5:2) 937#define CKG_S2_GOP_HDR_ODCLK (0 << 2) 938#define CKG_S2_GOP_HDR_EDCLK (1 << 2) 939 940#define REG_CKG_S2_MECLK (REG_CLKGEN2_BASE + 0x80 ) 941#define CKG_S2_MECLK_GATED BIT(0) 942#define CKG_S2_MECLK_INVERT BIT(1) 943#define CKG_S2_MECLK_MASK BMASK(5:2) 944 945#define REG_CKG_S2_MGCLK (REG_CLKGEN2_BASE + 0x82 ) 946#define CKG_S2_MGCLK_GATED BIT(0) 947#define CKG_S2_MGCLK_INVERT BIT(1) 948#define CKG_S2_MGCLK_MASK BMASK(5:2) 949 950#define CLK_SRC_IDCLK2 0 951#define CLK_SRC_FCLK 1 952#define CLK_SRC_XTAL 3 953 954#define MIU0_G0_REQUEST_MASK (REG_MIU0_BASE + 0x46) 955#define MIU0_G1_REQUEST_MASK (REG_MIU0_BASE + 0x66) 956#define MIU0_G2_REQUEST_MASK (REG_MIU0_BASE + 0x86) 957#define MIU0_G3_REQUEST_MASK (REG_MIU0_BASE + 0xA6) 958#define MIU0_G4_REQUEST_MASK (REG_MIU0_EX_BASE + 0x06) 959#define MIU0_G5_REQUEST_MASK (REG_MIU0_EX_BASE + 0x26) 960 961#define MIU1_G0_REQUEST_MASK (REG_MIU1_BASE + 0x46) 962#define MIU1_G1_REQUEST_MASK (REG_MIU1_BASE + 0x66) 963#define MIU1_G2_REQUEST_MASK (REG_MIU1_BASE + 0x86) 964#define MIU1_G3_REQUEST_MASK (REG_MIU1_BASE + 0xA6) 965#define MIU1_G4_REQUEST_MASK (REG_MIU1_EX_BASE + 0x06) 966#define MIU1_G5_REQUEST_MASK (REG_MIU1_EX_BASE + 0x26) 967 968#define MIU_SC0_G0REQUEST_MASK (0x0000) 969#define MIU_SC0_G1REQUEST_MASK (0x0000) 970#define MIU_SC0_G2REQUEST_MASK (0x0000) 971#define MIU_SC0_G3REQUEST_MASK (0x03C0) 972 973#define MIU_SC1_G0REQUEST_MASK (0x0000) 974#define MIU_SC1_G1REQUEST_MASK (0x0000) 975#define MIU_SC1_G2REQUEST_MASK (0x0000) 976#define MIU_SC1_G3REQUEST_MASK (0x0402) 977 978#define IP_DE_HSTART_MASK (0x1FFF) //BK_01_13 BK_03_13 979#define IP_DE_HEND_MASK (0x1FFF) //BK_01_15 BK_03_15 980#define IP_DE_VSTART_MASK (0x1FFF) //BK_01_12 BK_03_12 981#define IP_DE_VEND_MASK (0x1FFF) //BK_01_14 BK_03_14 982 983#define VOP_DE_HSTART_MASK (0x3FFF) //BK_10_04 984#define VOP_DE_HEND_MASK (0x3FFF) //BK_10_05 985#define VOP_DE_VSTART_MASK (0x1FFF) //BK_10_06 986#define VOP_DE_VEND_MASK (0x1FFF) //BK_10_07 987 988#define VOP_VTT_MASK (0x1FFF) //BK_10_0D 989#define VOP_HTT_MASK (0x3FFF) //BK_10_0C 990 991#define VOP_VSYNC_END_MASK (0x1FFF) //BK_10_03 992#define VOP_DISPLAY_HSTART_MASK (0x3FFF) //BK_10_08 993#define VOP_DISPLAY_HEND_MASK (0x3FFF) //BK_10_09 994#define VOP_DISPLAY_VSTART_MASK (0x1FFF) //BK_10_0A 995#define VOP_DISPLAY_VEND_MASK (0x1FFF) //BK_10_0B 996 997#define HW_DESIGN_LD_VER (1) 998 999#define FPLL_THRESH_MODE_SUPPORT 0 1000 1001#define ADC_CENTER_GAIN 0x1000 1002#define ADC_CENTER_OFFSET 0x0800 1003#define ADC_GAIN_BIT_CNT 14 1004#define ADC_OFFSET_BIT_CNT 13 1005 1006#define ADC_VGA_DEFAULT_GAIN_R 0x1000 1007#define ADC_VGA_DEFAULT_GAIN_G 0x1000 1008#define ADC_VGA_DEFAULT_GAIN_B 0x1000 1009#define ADC_VGA_DEFAULT_OFFSET_R 0x0000 1010#define ADC_VGA_DEFAULT_OFFSET_G 0x0000 1011#define ADC_VGA_DEFAULT_OFFSET_B 0x0000 1012#define ADC_YPBPR_DEFAULT_GAIN_R 0x1212 1013#define ADC_YPBPR_DEFAULT_GAIN_G 0x11AA 1014#define ADC_YPBPR_DEFAULT_GAIN_B 0x1212 1015#define ADC_YPBPR_DEFAULT_OFFSET_R 0x0800 1016#define ADC_YPBPR_DEFAULT_OFFSET_G 0x0100 1017#define ADC_YPBPR_DEFAULT_OFFSET_B 0x0800 1018#define ADC_SCART_DEFAULT_GAIN_R 0x1000 1019#define ADC_SCART_DEFAULT_GAIN_G 0x1000 1020#define ADC_SCART_DEFAULT_GAIN_B 0x1000 1021#define ADC_SCART_DEFAULT_OFFSET_R 0x0100 1022#define ADC_SCART_DEFAULT_OFFSET_G 0x0100 1023#define ADC_SCART_DEFAULT_OFFSET_B 0x0100 1024 1025/////////////////////////////////////////////// 1026// Enable Hardware auto gain/offset 1027#define ADC_HARDWARE_AUTOOFFSET_RGB ENABLE 1028#define ADC_HARDWARE_AUTOOFFSET_YPBPR ENABLE 1029#define ADC_HARDWARE_AUTOOFFSET_SCARTRGB ENABLE 1030#define ADC_HARDWARE_AUTOGAIN_SUPPORTED ENABLE 1031#define ADC_VGA_FIXED_GAIN_R 0x16A5 1032#define ADC_VGA_FIXED_GAIN_G 0x16A5 1033#define ADC_VGA_FIXED_GAIN_B 0x16A5 1034#define ADC_VGA_FIXED_OFFSET_R 0x0000 1035#define ADC_VGA_FIXED_OFFSET_G 0x0000 1036#define ADC_VGA_FIXED_OFFSET_B 0x0000 1037#define ADC_YPBPR_FIXED_GAIN_R 0x13E4 1038#define ADC_YPBPR_FIXED_GAIN_G 0x1372 1039#define ADC_YPBPR_FIXED_GAIN_B 0x13E4 1040#define ADC_YPBPR_FIXED_OFFSET_R 0x0800 1041#define ADC_YPBPR_FIXED_OFFSET_G 0x0100 1042#define ADC_YPBPR_FIXED_OFFSET_B 0x0800 1043#define ADC_SCART_FIXED_GAIN_R 0x16A5 1044#define ADC_SCART_FIXED_GAIN_G 0x16A5 1045#define ADC_SCART_FIXED_GAIN_B 0x16A5 1046#define ADC_SCART_FIXED_OFFSET_R 0x0000 1047#define ADC_SCART_FIXED_OFFSET_G 0x0000 1048#define ADC_SCART_FIXED_OFFSET_B 0x0000 1049 1050#endif /* MHAL_XC_CONFIG_H */ 1051 1052