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Searched refs:REG32_W (Results 1 – 25 of 50) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/security/hal/maserati/aesdma/
H A DhalAESDMA.c150 #define REG32_W(reg, value) do { \ macro
213 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , 0x00000000); // clear ctrl register in AESDMA_Reset()
214 …REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|(AESDMA_CTRL_SW_RST… in AESDMA_Reset()
215 …REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)&~(AESDMA_CTRL_SW_RS… in AESDMA_Reset()
220 REG32_W((REG32 *)(Reg_AESDMA+(i*8)), 0x00000000); in AESDMA_Reset()
223 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl), 0x00000000); in AESDMA_Reset()
226 REG32_W((&_PARSERCtrl[0].Parser_Pid1),0x00000000); in AESDMA_Reset()
227 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),0x00000000); in AESDMA_Reset()
233 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_L) , cipherkey[0]); in AESDMA_Set_CipherKey()
234 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_H) , cipherkey[1]); in AESDMA_Set_CipherKey()
[all …]
/utopia/UTPA2-700.0.x/modules/security/hal/M7821/aesdma/
H A DhalAESDMA.c150 #define REG32_W(reg, value) do { \ macro
213 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , 0x00000000); // clear ctrl register in AESDMA_Reset()
214 …REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|(AESDMA_CTRL_SW_RST… in AESDMA_Reset()
215 …REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)&~(AESDMA_CTRL_SW_RS… in AESDMA_Reset()
220 REG32_W((REG32 *)(Reg_AESDMA+(i*8)), 0x00000000); in AESDMA_Reset()
223 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl), 0x00000000); in AESDMA_Reset()
226 REG32_W((&_PARSERCtrl[0].Parser_Pid1),0x00000000); in AESDMA_Reset()
227 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),0x00000000); in AESDMA_Reset()
233 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_L) , cipherkey[0]); in AESDMA_Set_CipherKey()
234 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_H) , cipherkey[1]); in AESDMA_Set_CipherKey()
[all …]
/utopia/UTPA2-700.0.x/modules/security/hal/maxim/aesdma/
H A DhalAESDMA.c134 #define REG32_W(reg, value) do { \ macro
197 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , 0x00000000); // clear ctrl register in AESDMA_Reset()
198 …REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|(AESDMA_CTRL_SW_RST… in AESDMA_Reset()
199 …REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)&~(AESDMA_CTRL_SW_RS… in AESDMA_Reset()
204 REG32_W((REG32 *)(Reg_AESDMA+(i*8)), 0x00000000); in AESDMA_Reset()
207 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl), 0x00000000); in AESDMA_Reset()
210 REG32_W((&_PARSERCtrl[0].Parser_Pid1),0x00000000); in AESDMA_Reset()
211 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),0x00000000); in AESDMA_Reset()
217 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_L) , cipherkey[0]); in AESDMA_Set_CipherKey()
218 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_H) , cipherkey[1]); in AESDMA_Set_CipherKey()
[all …]
/utopia/UTPA2-700.0.x/modules/security/hal/M7621/aesdma/
H A DhalAESDMA.c134 #define REG32_W(reg, value) do { \ macro
197 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , 0x00000000); // clear ctrl register in AESDMA_Reset()
198 …REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|(AESDMA_CTRL_SW_RST… in AESDMA_Reset()
199 …REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)&~(AESDMA_CTRL_SW_RS… in AESDMA_Reset()
204 REG32_W((REG32 *)(Reg_AESDMA+(i*8)), 0x00000000); in AESDMA_Reset()
207 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl), 0x00000000); in AESDMA_Reset()
210 REG32_W((&_PARSERCtrl[0].Parser_Pid1),0x00000000); in AESDMA_Reset()
211 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),0x00000000); in AESDMA_Reset()
217 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_L) , cipherkey[0]); in AESDMA_Set_CipherKey()
218 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_H) , cipherkey[1]); in AESDMA_Set_CipherKey()
[all …]
/utopia/UTPA2-700.0.x/modules/security/hal/maldives/aesdma/
H A DhalAESDMA.c129 #define REG32_W(reg, value) do { \ macro
185 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , 0x00000000); // clear ctrl register in AESDMA_Reset()
186 …REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|(AESDMA_CTRL_SW_RST… in AESDMA_Reset()
187 …REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)&~(AESDMA_CTRL_SW_RS… in AESDMA_Reset()
192 REG32_W((REG32 *)(Reg_AESDMA+(i*8)), 0x00000000); in AESDMA_Reset()
195 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl), 0x00000000); in AESDMA_Reset()
198 REG32_W((&_PARSERCtrl[0].Parser_Pid1),0x01000000); in AESDMA_Reset()
199 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),0x00000000); in AESDMA_Reset()
204 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_L) , cipherkey[0]); in AESDMA_Set_CipherKey()
205 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_H) , cipherkey[1]); in AESDMA_Set_CipherKey()
[all …]
/utopia/UTPA2-700.0.x/modules/security/hal/macan/aesdma/
H A DhalAESDMA.c135 #define REG32_W(reg, value) do { \ macro
195 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , 0x00000000); // clear ctrl register in AESDMA_Reset()
196 …REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|(AESDMA_CTRL_SW_RST… in AESDMA_Reset()
197 …REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)&~(AESDMA_CTRL_SW_RS… in AESDMA_Reset()
202 REG32_W((REG32 *)(Reg_AESDMA+(i*8)), 0x00000000); in AESDMA_Reset()
205 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl), 0x00000000); in AESDMA_Reset()
208 REG32_W((&_PARSERCtrl[0].Parser_Pid1),0x00000000); in AESDMA_Reset()
209 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),0x00000000); in AESDMA_Reset()
214 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_L) , cipherkey[0]); in AESDMA_Set_CipherKey()
215 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_H) , cipherkey[1]); in AESDMA_Set_CipherKey()
[all …]
/utopia/UTPA2-700.0.x/modules/security/hal/mooney/aesdma/
H A DhalAESDMA.c130 #define REG32_W(reg, value) do { \ macro
187 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , 0x00000000); // clear ctrl register in AESDMA_Reset()
188 …REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|(AESDMA_CTRL_SW_RST… in AESDMA_Reset()
189 …REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)&~(AESDMA_CTRL_SW_RS… in AESDMA_Reset()
194 REG32_W((REG32 *)(Reg_AESDMA+(i*8)), 0x00000000); in AESDMA_Reset()
197 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl), 0x00000000); in AESDMA_Reset()
200 REG32_W((&_PARSERCtrl[0].Parser_Pid1),0x01000000); in AESDMA_Reset()
201 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),0x00000000); in AESDMA_Reset()
206 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_L) , cipherkey[0]); in AESDMA_Set_CipherKey()
207 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_H) , cipherkey[1]); in AESDMA_Set_CipherKey()
[all …]
/utopia/UTPA2-700.0.x/modules/security/hal/mustang/aesdma/
H A DhalAESDMA.c129 #define REG32_W(reg, value) do { \ macro
185 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , 0x00000000); // clear ctrl register in AESDMA_Reset()
186 …REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|(AESDMA_CTRL_SW_RST… in AESDMA_Reset()
187 …REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)&~(AESDMA_CTRL_SW_RS… in AESDMA_Reset()
192 REG32_W((REG32 *)(Reg_AESDMA+(i*8)), 0x00000000); in AESDMA_Reset()
195 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl), 0x00000000); in AESDMA_Reset()
198 REG32_W((&_PARSERCtrl[0].Parser_Pid1),0x01000000); in AESDMA_Reset()
199 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),0x00000000); in AESDMA_Reset()
204 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_L) , cipherkey[0]); in AESDMA_Set_CipherKey()
205 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_H) , cipherkey[1]); in AESDMA_Set_CipherKey()
[all …]
/utopia/UTPA2-700.0.x/modules/security/hal/mainz/aesdma/
H A DhalAESDMA.c134 #define REG32_W(reg, value) do { \ macro
192 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , 0x00000000); // clear ctrl register in AESDMA_Reset()
193 …REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|(AESDMA_CTRL_SW_RST… in AESDMA_Reset()
194 …REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)&~(AESDMA_CTRL_SW_RS… in AESDMA_Reset()
199 REG32_W((REG32 *)(Reg_AESDMA+(i*8)), 0x00000000); in AESDMA_Reset()
202 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl), 0x00000000); in AESDMA_Reset()
205 REG32_W((&_PARSERCtrl[0].Parser_Pid1),0x01000000); in AESDMA_Reset()
206 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),0x00000000); in AESDMA_Reset()
211 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_L) , cipherkey[0]); in AESDMA_Set_CipherKey()
212 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_H) , cipherkey[1]); in AESDMA_Set_CipherKey()
[all …]
/utopia/UTPA2-700.0.x/modules/security/hal/manhattan/aesdma/
H A DhalAESDMA.c134 #define REG32_W(reg, value) do { \ macro
195 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , 0x00000000); // clear ctrl register in AESDMA_Reset()
196 …REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|(AESDMA_CTRL_SW_RST… in AESDMA_Reset()
197 …REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)&~(AESDMA_CTRL_SW_RS… in AESDMA_Reset()
202 REG32_W((REG32 *)(Reg_AESDMA+(i*8)), 0x00000000); in AESDMA_Reset()
205 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl), 0x00000000); in AESDMA_Reset()
208 REG32_W((&_PARSERCtrl[0].Parser_Pid1),0x00000000); in AESDMA_Reset()
209 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),0x00000000); in AESDMA_Reset()
214 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_L) , cipherkey[0]); in AESDMA_Set_CipherKey()
215 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_H) , cipherkey[1]); in AESDMA_Set_CipherKey()
[all …]
/utopia/UTPA2-700.0.x/modules/security/hal/messi/aesdma/
H A DhalAESDMA.c134 #define REG32_W(reg, value) do { \ macro
192 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , 0x00000000); // clear ctrl register in AESDMA_Reset()
193 …REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|(AESDMA_CTRL_SW_RST… in AESDMA_Reset()
194 …REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)&~(AESDMA_CTRL_SW_RS… in AESDMA_Reset()
199 REG32_W((REG32 *)(Reg_AESDMA+(i*8)), 0x00000000); in AESDMA_Reset()
202 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl), 0x00000000); in AESDMA_Reset()
205 REG32_W((&_PARSERCtrl[0].Parser_Pid1),0x01000000); in AESDMA_Reset()
206 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),0x00000000); in AESDMA_Reset()
211 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_L) , cipherkey[0]); in AESDMA_Set_CipherKey()
212 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_H) , cipherkey[1]); in AESDMA_Set_CipherKey()
[all …]
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/dscmb/
H A DhalDSCMB.c703 static void REG32_W(MS_VIRT u32Reg, MS_U32 u32Value) in REG32_W() function
722 REG32_W(u32Reg, u32Value); in REG16_W()
916 REG32_W(REG_CIPHER_CSA2_CTRL(0), u32Tmp); in HAL_DSCMB_Init()
922 REG32_W(REG_TSCE_CTRL, u32Tmp); in HAL_DSCMB_Init()
929 REG32_W(REG_TSP_PID_SLOT_MAP_NO, u32Tmp); in HAL_DSCMB_Init()
952 REG32_W(REG_PIDIDX_WRITE_DATA , REG_PIDIDX_WDATA_MSK & u32wdata ); in _HAL_DSCMB_PidIdx_MuxWrite()
954 REG32_W(REG_PIDIDX_CTRL , u32Tmp | REG_PIDIDX_CMD_GO ); in _HAL_DSCMB_PidIdx_MuxWrite()
979 REG32_W(REG_PIDIDX_CTRL , u32Tmp | REG_PIDIDX_CMD_GO ); in _HAL_DSCMB_PidIdx_MuxRead()
1011 REG32_W(REG_PIDIDX_CTRL , u32Tmp | REG_PIDIDX_CMD_GO ); in _HAL_DSCMB_PidIdx_MuxRead_FPGA()
1178 REG32_W(REG_KTE_DATA0, u32data[0] ); in _HAL_DSCMB_KTE_Write_Ex()
[all …]
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/dscmb/
H A DhalDSCMB.c703 static void REG32_W(MS_VIRT u32Reg, MS_U32 u32Value) in REG32_W() function
722 REG32_W(u32Reg, u32Value); in REG16_W()
918 REG32_W(REG_CIPHER_CSA2_CTRL(0), u32Tmp); in HAL_DSCMB_Init()
925 REG32_W(REG_TSCE_CTRL, u32Tmp); in HAL_DSCMB_Init()
933 REG32_W(REG_TSP_PID_SLOT_MAP_NO, u32Tmp); in HAL_DSCMB_Init()
956 REG32_W(REG_PIDIDX_WRITE_DATA , REG_PIDIDX_WDATA_MSK & u32wdata ); in _HAL_DSCMB_PidIdx_MuxWrite()
958 REG32_W(REG_PIDIDX_CTRL , u32Tmp | REG_PIDIDX_CMD_GO ); in _HAL_DSCMB_PidIdx_MuxWrite()
983 REG32_W(REG_PIDIDX_CTRL , u32Tmp | REG_PIDIDX_CMD_GO ); in _HAL_DSCMB_PidIdx_MuxRead()
1015 REG32_W(REG_PIDIDX_CTRL , u32Tmp | REG_PIDIDX_CMD_GO ); in _HAL_DSCMB_PidIdx_MuxRead_FPGA()
1182 REG32_W(REG_KTE_DATA0, u32data[0] ); in _HAL_DSCMB_KTE_Write_Ex()
[all …]
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/dscmb/
H A DhalDSCMB.c697 static void REG32_W(MS_VIRT u32Reg, MS_U32 u32Value) in REG32_W() function
716 REG32_W(u32Reg, u32Value); in REG16_W()
910 REG32_W(REG_CIPHER_CSA2_CTRL(0), u32Tmp); in HAL_DSCMB_Init()
916 REG32_W(REG_TSCE_CTRL, u32Tmp); in HAL_DSCMB_Init()
923 REG32_W(REG_TSP_PID_SLOT_MAP_NO, u32Tmp); in HAL_DSCMB_Init()
946 REG32_W(REG_PIDIDX_WRITE_DATA , REG_PIDIDX_WDATA_MSK & u32wdata ); in _HAL_DSCMB_PidIdx_MuxWrite()
948 REG32_W(REG_PIDIDX_CTRL , u32Tmp | REG_PIDIDX_CMD_GO ); in _HAL_DSCMB_PidIdx_MuxWrite()
973 REG32_W(REG_PIDIDX_CTRL , u32Tmp | REG_PIDIDX_CMD_GO ); in _HAL_DSCMB_PidIdx_MuxRead()
1005 REG32_W(REG_PIDIDX_CTRL , u32Tmp | REG_PIDIDX_CMD_GO ); in _HAL_DSCMB_PidIdx_MuxRead_FPGA()
1172 REG32_W(REG_KTE_DATA0, u32data[0] ); in _HAL_DSCMB_KTE_Write_Ex()
[all …]
/utopia/UTPA2-700.0.x/modules/dscmb/hal/curry/dscmb/
H A DhalDSCMB.c689 static void REG32_W(MS_VIRT u32Reg, MS_U32 u32Value) in REG32_W() function
703 REG32_W(u32Reg, u32Value); in REG16_W()
918 REG32_W(REG_CIPHER_CSA2_CTRL(0), u32Tmp); in HAL_DSCMB_Init()
924 REG32_W(REG_TSCE_CTRL, u32Tmp); in HAL_DSCMB_Init()
931 REG32_W(REG_TSP_PID_SLOT_MAP_NO, u32Tmp); in HAL_DSCMB_Init()
957 REG32_W(REG_PIDIDX_WRITE_DATA , REG_PIDIDX_WDATA_MSK & u32wdata ); in _HAL_DSCMB_PidIdx_MuxWrite()
959 REG32_W(REG_PIDIDX_CTRL , u32Tmp | REG_PIDIDX_CMD_GO ); in _HAL_DSCMB_PidIdx_MuxWrite()
984 REG32_W(REG_PIDIDX_CTRL , u32Tmp | REG_PIDIDX_CMD_GO ); in _HAL_DSCMB_PidIdx_MuxRead()
1015 REG32_W(REG_PIDIDX_CTRL , u32Tmp | REG_PIDIDX_CMD_GO ); in _HAL_DSCMB_PidIdx_MuxRead_FPGA()
1193 REG32_W(REG_KTE_DATA0, u32data[0] ); in _HAL_DSCMB_KTE_Write_Ex()
[all …]
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/dscmb/
H A DhalDSCMB.c689 static void REG32_W(MS_VIRT u32Reg, MS_U32 u32Value) in REG32_W() function
703 REG32_W(u32Reg, u32Value); in REG16_W()
918 REG32_W(REG_CIPHER_CSA2_CTRL(0), u32Tmp); in HAL_DSCMB_Init()
924 REG32_W(REG_TSCE_CTRL, u32Tmp); in HAL_DSCMB_Init()
931 REG32_W(REG_TSP_PID_SLOT_MAP_NO, u32Tmp); in HAL_DSCMB_Init()
957 REG32_W(REG_PIDIDX_WRITE_DATA , REG_PIDIDX_WDATA_MSK & u32wdata ); in _HAL_DSCMB_PidIdx_MuxWrite()
959 REG32_W(REG_PIDIDX_CTRL , u32Tmp | REG_PIDIDX_CMD_GO ); in _HAL_DSCMB_PidIdx_MuxWrite()
984 REG32_W(REG_PIDIDX_CTRL , u32Tmp | REG_PIDIDX_CMD_GO ); in _HAL_DSCMB_PidIdx_MuxRead()
1015 REG32_W(REG_PIDIDX_CTRL , u32Tmp | REG_PIDIDX_CMD_GO ); in _HAL_DSCMB_PidIdx_MuxRead_FPGA()
1193 REG32_W(REG_KTE_DATA0, u32data[0] ); in _HAL_DSCMB_KTE_Write_Ex()
[all …]
/utopia/UTPA2-700.0.x/modules/cmdq/hal/k6lite/cmdq/
H A DhalCMDQ.c143 #define REG32_W(reg, value) do { \ macro
195 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Enable), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Enable) | (CMDQ_CMDQ_E… in HAL_CMDQ_Enable()
196 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Length_ReadMode), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Length_ReadMo… in HAL_CMDQ_Enable()
197 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Mask_Setting), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Mask_Setting) | … in HAL_CMDQ_Enable()
200 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Tout_Base_Amount) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Tout_Base_A… in HAL_CMDQ_Enable()
205 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Enable), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Enable) | (CMDQ_CMDQ_D… in HAL_CMDQ_Stop()
214 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_En_Clk_Miu), (_CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_En_Clk_Miu) & (~C… in HAL_CMDQ_Reset()
215 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_En_Clk_Miu), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_En_Clk_Miu) | (CMD… in HAL_CMDQ_Reset()
222 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) | (CMDQ… in HAL_CMDQ_Set_Mode()
227 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) | (CMDQ… in HAL_CMDQ_Set_Mode()
[all …]
/utopia/UTPA2-700.0.x/modules/cmdq/hal/k6/cmdq/
H A DhalCMDQ.c144 #define REG32_W(reg, value) do { \ macro
196 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Enable), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Enable) | (CMDQ_CMDQ_E… in HAL_CMDQ_Enable()
197 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Length_ReadMode), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Length_ReadMo… in HAL_CMDQ_Enable()
198 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Mask_Setting), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Mask_Setting) | … in HAL_CMDQ_Enable()
201 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Tout_Base_Amount) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Tout_Base_A… in HAL_CMDQ_Enable()
208 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Enable), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Enable) | (CMDQ_CMDQ_D… in HAL_CMDQ_Stop()
217 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_En_Clk_Miu), (_CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_En_Clk_Miu) & (~C… in HAL_CMDQ_Reset()
218 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_En_Clk_Miu), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_En_Clk_Miu) | (CMD… in HAL_CMDQ_Reset()
225 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) | (CMDQ… in HAL_CMDQ_Set_Mode()
230 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) | (CMDQ… in HAL_CMDQ_Set_Mode()
[all …]
/utopia/UTPA2-700.0.x/modules/cmdq/hal/curry/cmdq/
H A DhalCMDQ.c144 #define REG32_W(reg, value) do { \ macro
202 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Enable), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Enable) | (CMDQ_CMDQ_E… in HAL_CMDQ_Enable()
203 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Length_ReadMode), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Length_ReadMo… in HAL_CMDQ_Enable()
204 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Mask_Setting), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Mask_Setting) | … in HAL_CMDQ_Enable()
207 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Tout_Base_Amount) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Tout_Base_A… in HAL_CMDQ_Enable()
212 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Enable), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Enable) | (CMDQ_CMDQ_D… in HAL_CMDQ_Stop()
221 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_En_Clk_Miu), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_En_Clk_Miu) | (CMD… in HAL_CMDQ_Reset()
228 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) | (CMDQ… in HAL_CMDQ_Set_Mode()
233 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) | (CMDQ… in HAL_CMDQ_Set_Mode()
238 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) | (CMDQ… in HAL_CMDQ_Set_Mode()
[all …]
/utopia/UTPA2-700.0.x/modules/cmdq/hal/kano/cmdq/
H A DhalCMDQ.c144 #define REG32_W(reg, value) do { \ macro
202 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Enable), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Enable) | (CMDQ_CMDQ_E… in HAL_CMDQ_Enable()
203 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Length_ReadMode), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Length_ReadMo… in HAL_CMDQ_Enable()
204 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Mask_Setting), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Mask_Setting) | … in HAL_CMDQ_Enable()
207 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Tout_Base_Amount) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Tout_Base_A… in HAL_CMDQ_Enable()
212 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Enable), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Enable) | (CMDQ_CMDQ_D… in HAL_CMDQ_Stop()
221 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_En_Clk_Miu), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_En_Clk_Miu) | (CMD… in HAL_CMDQ_Reset()
228 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) | (CMDQ… in HAL_CMDQ_Set_Mode()
233 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) | (CMDQ… in HAL_CMDQ_Set_Mode()
238 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) | (CMDQ… in HAL_CMDQ_Set_Mode()
[all …]
/utopia/UTPA2-700.0.x/modules/cmdq/hal/maxim/cmdq/
H A DhalCMDQ.c140 #define REG32_W(reg, value) do { \ macro
196 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Enable), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Enable) | (CMDQ_CMDQ_E… in HAL_CMDQ_Enable()
197 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Length_ReadMode), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Length_ReadMo… in HAL_CMDQ_Enable()
198 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Mask_Setting), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Mask_Setting) | … in HAL_CMDQ_Enable()
201 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Tout_Base_Amount) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Tout_Base_A… in HAL_CMDQ_Enable()
206 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Enable), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Enable) | (CMDQ_CMDQ_D… in HAL_CMDQ_Stop()
215 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_En_Clk_Miu), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_En_Clk_Miu) | (CMD… in HAL_CMDQ_Reset()
222 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) | (CMDQ… in HAL_CMDQ_Set_Mode()
227 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) | (CMDQ… in HAL_CMDQ_Set_Mode()
232 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) | (CMDQ… in HAL_CMDQ_Set_Mode()
[all …]
/utopia/UTPA2-700.0.x/modules/cmdq/hal/M7621/cmdq/
H A DhalCMDQ.c140 #define REG32_W(reg, value) do { \ macro
196 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Enable), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Enable) | (CMDQ_CMDQ_E… in HAL_CMDQ_Enable()
197 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Length_ReadMode), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Length_ReadMo… in HAL_CMDQ_Enable()
198 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Mask_Setting), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Mask_Setting) | … in HAL_CMDQ_Enable()
201 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Tout_Base_Amount) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Tout_Base_A… in HAL_CMDQ_Enable()
206 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Enable), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Enable) | (CMDQ_CMDQ_D… in HAL_CMDQ_Stop()
215 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_En_Clk_Miu), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_En_Clk_Miu) | (CMD… in HAL_CMDQ_Reset()
222 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) | (CMDQ… in HAL_CMDQ_Set_Mode()
227 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) | (CMDQ… in HAL_CMDQ_Set_Mode()
232 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) | (CMDQ… in HAL_CMDQ_Set_Mode()
[all …]
/utopia/UTPA2-700.0.x/modules/cmdq/hal/manhattan/cmdq/
H A DhalCMDQ.c138 #define REG32_W(reg, value) do { \ macro
190 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Enable), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Enable) | (CMDQ_CMDQ_E… in HAL_CMDQ_Enable()
191 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Length_ReadMode), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Length_ReadMo… in HAL_CMDQ_Enable()
192 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Mask_Setting), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Mask_Setting) | … in HAL_CMDQ_Enable()
195 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Tout_Base_Amount) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Tout_Base_A… in HAL_CMDQ_Enable()
200 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Enable), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Enable) | (CMDQ_CMDQ_D… in HAL_CMDQ_Stop()
209 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_En_Clk_Miu), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_En_Clk_Miu) | (CMD… in HAL_CMDQ_Reset()
216 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) | (CMDQ… in HAL_CMDQ_Set_Mode()
221 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) | (CMDQ… in HAL_CMDQ_Set_Mode()
226 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) | (CMDQ… in HAL_CMDQ_Set_Mode()
[all …]
/utopia/UTPA2-700.0.x/modules/cmdq/hal/M7821/cmdq/
H A DhalCMDQ.c165 #define REG32_W(reg, value) do { \ macro
224 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Enable), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Enable) | (CMDQ_CMDQ_E… in HAL_CMDQ_Enable()
225 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Length_ReadMode), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Length_ReadMo… in HAL_CMDQ_Enable()
226 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Mask_Setting), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Mask_Setting) | … in HAL_CMDQ_Enable()
229 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Tout_Base_Amount) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Tout_Base_A… in HAL_CMDQ_Enable()
234 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Enable), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Enable) | (CMDQ_CMDQ_D… in HAL_CMDQ_Stop()
243 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_En_Clk_Miu), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_En_Clk_Miu) | (CMD… in HAL_CMDQ_Reset()
250 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) | (CMDQ… in HAL_CMDQ_Set_Mode()
255 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) | (CMDQ… in HAL_CMDQ_Set_Mode()
260 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) | (CMDQ… in HAL_CMDQ_Set_Mode()
[all …]
/utopia/UTPA2-700.0.x/modules/cmdq/hal/maserati/cmdq/
H A DhalCMDQ.c165 #define REG32_W(reg, value) do { \ macro
224 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Enable), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Enable) | (CMDQ_CMDQ_E… in HAL_CMDQ_Enable()
225 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Length_ReadMode), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Length_ReadMo… in HAL_CMDQ_Enable()
226 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Mask_Setting), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Mask_Setting) | … in HAL_CMDQ_Enable()
229 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Tout_Base_Amount) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Tout_Base_A… in HAL_CMDQ_Enable()
234 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Enable), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Enable) | (CMDQ_CMDQ_D… in HAL_CMDQ_Stop()
243 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_En_Clk_Miu), _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_En_Clk_Miu) | (CMD… in HAL_CMDQ_Reset()
250 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) | (CMDQ… in HAL_CMDQ_Set_Mode()
255 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) | (CMDQ… in HAL_CMDQ_Set_Mode()
260 …REG32_W((&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[hnd]->CMDQ_Trig_Mode) | (CMDQ… in HAL_CMDQ_Set_Mode()
[all …]

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