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Searched refs:L_BK_CLKGEN0 (Results 1 – 25 of 40) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/vd/hal/mainz/avd/
H A DhalAVD.c2971 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
2977 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2980 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2983 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2986 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2989 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2992 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2995 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2998 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
3001 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/mustang/avd/
H A DhalAVD.c6315 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
6321 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6324 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6327 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6330 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6333 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6336 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6339 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6342 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6345 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/M7821/avd/
H A DhalAVD.c6330 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
6336 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6339 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6342 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6345 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6348 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6351 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6354 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6357 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6360 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/kano/avd/
H A DhalAVD.c6330 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
6336 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6339 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6342 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6345 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6348 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6351 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6354 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6357 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6360 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/manhattan/avd/
H A DhalAVD.c6329 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
6335 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6338 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6341 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6344 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6347 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6350 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6353 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6356 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6359 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/M7621/avd/
H A DhalAVD.c6330 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
6336 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6339 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6342 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6345 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6348 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6351 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6354 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6357 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6360 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/maldives/avd/
H A DhalAVD.c6315 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
6321 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6324 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6327 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6330 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6333 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6336 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6339 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6342 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6345 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/messi/avd/
H A DhalAVD.c2971 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
2977 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2980 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2983 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2986 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2989 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2992 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2995 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2998 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
3001 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/maserati/avd/
H A DhalAVD.c6330 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
6336 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6339 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6342 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6345 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6348 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6351 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6354 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6357 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6360 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/maxim/avd/
H A DhalAVD.c6330 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
6336 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6339 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6342 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6345 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6348 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6351 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6354 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6357 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6360 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/mooney/avd/
H A DhalAVD.c2970 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
2976 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2979 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2982 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2985 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2988 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2991 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2994 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
2997 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
3000 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/macan/avd/
H A DhalAVD.c6317 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
6323 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6326 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6329 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6332 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6335 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6338 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6341 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6344 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6347 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
[all …]
/utopia/UTPA2-700.0.x/modules/ve/hal/maxim/ve/
H A Dmhal_tvencoder.c300 MDrv_WriteByteMask(L_BK_CLKGEN0(0x24), 0x00, 0x0f); // clock of ve in Hal_VE_init()
935 MDrv_WriteByte(L_BK_CLKGEN0(0x25), u8clk); // idclk in Hal_VE_set_mux()
937 MDrv_WriteRegBit(L_BK_CLKGEN0(0x5a), BIT(4), BIT(4)); // CLK_VE_IN setting user mode in Hal_VE_set_mux()
976 MDrv_WriteByteMask(L_BK_CLKGEN0(0x25), !ben, 0x01); // clock of vein Ena/disable in Hal_VE_set_clk_on_off()
1021 MDrv_WriteByteMask(L_BK_CLKGEN0(0x25), !ben, 0x01); // clock of vein Ena/disable in Hal_VE_set_clk_on_off()
1022 MDrv_WriteByteMask(L_BK_CLKGEN0(0x24), !ben, 0x01); // clock of ve Ena/disable in Hal_VE_set_clk_on_off()
/utopia/UTPA2-700.0.x/modules/ve/hal/maserati/ve/
H A Dmhal_tvencoder.c299 MDrv_WriteByteMask(L_BK_CLKGEN0(0x24), 0x00, 0x0f); // clock of ve in Hal_VE_init()
934 MDrv_WriteByte(L_BK_CLKGEN0(0x25), u8clk); // idclk in Hal_VE_set_mux()
936 MDrv_WriteRegBit(L_BK_CLKGEN0(0x5a), BIT(4), BIT(4)); // CLK_VE_IN setting user mode in Hal_VE_set_mux()
975 MDrv_WriteByteMask(L_BK_CLKGEN0(0x25), !ben, 0x01); // clock of vein Ena/disable in Hal_VE_set_clk_on_off()
1020 MDrv_WriteByteMask(L_BK_CLKGEN0(0x25), !ben, 0x01); // clock of vein Ena/disable in Hal_VE_set_clk_on_off()
1021 MDrv_WriteByteMask(L_BK_CLKGEN0(0x24), !ben, 0x01); // clock of ve Ena/disable in Hal_VE_set_clk_on_off()
/utopia/UTPA2-700.0.x/modules/ve/hal/M7621/ve/
H A Dmhal_tvencoder.c300 MDrv_WriteByteMask(L_BK_CLKGEN0(0x24), 0x00, 0x0f); // clock of ve in Hal_VE_init()
935 MDrv_WriteByte(L_BK_CLKGEN0(0x25), u8clk); // idclk in Hal_VE_set_mux()
937 MDrv_WriteRegBit(L_BK_CLKGEN0(0x5a), BIT(4), BIT(4)); // CLK_VE_IN setting user mode in Hal_VE_set_mux()
976 MDrv_WriteByteMask(L_BK_CLKGEN0(0x25), !ben, 0x01); // clock of vein Ena/disable in Hal_VE_set_clk_on_off()
1021 MDrv_WriteByteMask(L_BK_CLKGEN0(0x25), !ben, 0x01); // clock of vein Ena/disable in Hal_VE_set_clk_on_off()
1022 MDrv_WriteByteMask(L_BK_CLKGEN0(0x24), !ben, 0x01); // clock of ve Ena/disable in Hal_VE_set_clk_on_off()
/utopia/UTPA2-700.0.x/modules/ve/hal/M7821/ve/
H A Dmhal_tvencoder.c299 MDrv_WriteByteMask(L_BK_CLKGEN0(0x24), 0x00, 0x0f); // clock of ve in Hal_VE_init()
934 MDrv_WriteByte(L_BK_CLKGEN0(0x25), u8clk); // idclk in Hal_VE_set_mux()
936 MDrv_WriteRegBit(L_BK_CLKGEN0(0x5a), BIT(4), BIT(4)); // CLK_VE_IN setting user mode in Hal_VE_set_mux()
975 MDrv_WriteByteMask(L_BK_CLKGEN0(0x25), !ben, 0x01); // clock of vein Ena/disable in Hal_VE_set_clk_on_off()
1020 MDrv_WriteByteMask(L_BK_CLKGEN0(0x25), !ben, 0x01); // clock of vein Ena/disable in Hal_VE_set_clk_on_off()
1021 MDrv_WriteByteMask(L_BK_CLKGEN0(0x24), !ben, 0x01); // clock of ve Ena/disable in Hal_VE_set_clk_on_off()
/utopia/UTPA2-700.0.x/modules/ve/hal/macan/ve/
H A Dmhal_tvencoder.c292 MDrv_WriteByteMask(L_BK_CLKGEN0(0x24), 0x00, 0x0f); // clock of ve in Hal_VE_init()
929 MDrv_WriteByte(L_BK_CLKGEN0(0x25), u8clk); // idclk in Hal_VE_set_mux()
931 MDrv_WriteRegBit(L_BK_CLKGEN0(0x5a), BIT(4), BIT(4)); // CLK_VE_IN setting user mode in Hal_VE_set_mux()
967 MDrv_WriteByteMask(L_BK_CLKGEN0(0x25), !ben, 0x01); // clock of vein Ena/disable in Hal_VE_set_clk_on_off()
968 MDrv_WriteByteMask(L_BK_CLKGEN0(0x24), !ben, 0x01); // clock of ve Ena/disable in Hal_VE_set_clk_on_off()
/utopia/UTPA2-700.0.x/modules/ve/hal/manhattan/ve/
H A Dmhal_tvencoder.c296 MDrv_WriteByteMask(L_BK_CLKGEN0(0x24), 0x00, 0x0f); // clock of ve in Hal_VE_init()
931 MDrv_WriteByte(L_BK_CLKGEN0(0x25), u8clk); // idclk in Hal_VE_set_mux()
933 MDrv_WriteRegBit(L_BK_CLKGEN0(0x5a), BIT(4), BIT(4)); // CLK_VE_IN setting user mode in Hal_VE_set_mux()
969 MDrv_WriteByteMask(L_BK_CLKGEN0(0x25), !ben, 0x01); // clock of vein Ena/disable in Hal_VE_set_clk_on_off()
970 MDrv_WriteByteMask(L_BK_CLKGEN0(0x24), !ben, 0x01); // clock of ve Ena/disable in Hal_VE_set_clk_on_off()
/utopia/UTPA2-700.0.x/modules/ve/hal/mustang/ve/
H A Dmhal_tvencoder.c290 MDrv_WriteByteMask(L_BK_CLKGEN0(0x24), 0x00, 0x0f); // clock of ve in Hal_VE_init()
917 MDrv_WriteByte(L_BK_CLKGEN0(0x25), u8clk); // idclk in Hal_VE_set_mux()
947 MDrv_WriteByteMask(L_BK_CLKGEN0(0x25), !ben, 0x01); // clock of vein Ena/disable in Hal_VE_set_clk_on_off()
948 MDrv_WriteByteMask(L_BK_CLKGEN0(0x24), !ben, 0x01); // clock of ve Ena/disable in Hal_VE_set_clk_on_off()
/utopia/UTPA2-700.0.x/modules/ve/hal/maldives/ve/
H A Dmhal_tvencoder.c290 MDrv_WriteByteMask(L_BK_CLKGEN0(0x24), 0x00, 0x0f); // clock of ve in Hal_VE_init()
915 MDrv_WriteByte(L_BK_CLKGEN0(0x25), u8clk); // idclk in Hal_VE_set_mux()
945 MDrv_WriteByteMask(L_BK_CLKGEN0(0x25), !ben, 0x01); // clock of vein Ena/disable in Hal_VE_set_clk_on_off()
946 MDrv_WriteByteMask(L_BK_CLKGEN0(0x24), !ben, 0x01); // clock of ve Ena/disable in Hal_VE_set_clk_on_off()
/utopia/UTPA2-700.0.x/modules/ve/hal/mainz/ve/
H A Dmhal_tvencoder.c293 MDrv_WriteByteMask(L_BK_CLKGEN0(0x24), 0x00, 0x0f); // clock of ve in Hal_VE_init()
925 MDrv_WriteByte(L_BK_CLKGEN0(0x25), u8clk); // idclk in Hal_VE_set_mux()
963 MDrv_WriteByteMask(L_BK_CLKGEN0(0x25), !ben, 0x01); // clock of vein Ena/disable in Hal_VE_set_clk_on_off()
964 MDrv_WriteByteMask(L_BK_CLKGEN0(0x24), !ben, 0x01); // clock of ve Ena/disable in Hal_VE_set_clk_on_off()
/utopia/UTPA2-700.0.x/modules/ve/hal/messi/ve/
H A Dmhal_tvencoder.c293 MDrv_WriteByteMask(L_BK_CLKGEN0(0x24), 0x00, 0x0f); // clock of ve in Hal_VE_init()
925 MDrv_WriteByte(L_BK_CLKGEN0(0x25), u8clk); // idclk in Hal_VE_set_mux()
963 MDrv_WriteByteMask(L_BK_CLKGEN0(0x25), !ben, 0x01); // clock of vein Ena/disable in Hal_VE_set_clk_on_off()
964 MDrv_WriteByteMask(L_BK_CLKGEN0(0x24), !ben, 0x01); // clock of ve Ena/disable in Hal_VE_set_clk_on_off()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_frc.c1231 W2BYTEMSK(L_BK_CLKGEN0(0x53),0x00,0x02); // Not Invert in MHal_FRC_ByPass_Enable()
1232 W2BYTEMSK(L_BK_CLKGEN0(0x53),0x00,0x01); // Enable clock in MHal_FRC_ByPass_Enable()
1234 W2BYTEMSK(L_BK_CLKGEN0(0x53),0xC0C,0xC0C); // LPLL output clock in MHal_FRC_ByPass_Enable()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_frc.c1576 W2BYTEMSK(L_BK_CLKGEN0(0x53),0x00,0x02); // Not Invert in MHal_FRC_ByPass_Enable()
1577 W2BYTEMSK(L_BK_CLKGEN0(0x53),0x00,0x01); // Enable clock in MHal_FRC_ByPass_Enable()
1579 W2BYTEMSK(L_BK_CLKGEN0(0x53),0xC0C,0xC0C); // LPLL output clock in MHal_FRC_ByPass_Enable()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_frc.c1559 W2BYTEMSK(L_BK_CLKGEN0(0x53),0x00,0x02); // Not Invert in MHal_FRC_ByPass_Enable()
1560 W2BYTEMSK(L_BK_CLKGEN0(0x53),0x00,0x01); // Enable clock in MHal_FRC_ByPass_Enable()
1562 W2BYTEMSK(L_BK_CLKGEN0(0x53),0xC0C,0xC0C); // LPLL output clock in MHal_FRC_ByPass_Enable()

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