6330 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2));  // 20090628 BY put mailbo0 clock sett…  in HAL_AVD_VDMCU_SetClock()
6336             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
6339             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
6342             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
6345             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
6348             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
6351             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
6354             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
6357             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3)|BIT(2), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
6360             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
6366         RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BIT(1));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
6370         RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(1), BIT(1));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
6394 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2));  // 20090628 BY put mailbo0 clock sett…  in HAL_AVD_VDMCU_SetClock()
6400             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3)|BIT(2), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
6403             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
6406             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
6409             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
6412             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
6415             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
6418             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
6421             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
6424             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
6430         RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BIT(1));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
6434         RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(1), BIT(1));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
6944     RIU_WriteRegBit (L_BK_CLKGEN0(0x21), bEnable, BIT(0)); // CLK_VDMCU, 0:Enable 1:Disable  in HAL_AVD_AFEC_SetClock()
6948     RIU_WriteByteMask (L_BK_CLKGEN0(0x22), 0x00, BMASK(3:0));// CLK_mailbox0  in HAL_AVD_AFEC_SetClock()
6950     RIU_WriteRegBit (L_BK_CLKGEN0(0x23), bEnable, BIT(0));// CLK_VD2X  in HAL_AVD_AFEC_SetClock()
6984         RIU_WriteRegBit(L_BK_CLKGEN0(0x00), DISABLE, BIT(4));  in HAL_AVD_AFEC_SetClockSource()
7007         RIU_WriteRegBit(L_BK_CLKGEN0(0x00), ENABLE, BIT(4));  in HAL_AVD_AFEC_SetClockSource()