2971 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2));  // 20090628 BY put mailbo0 clock sett…  in HAL_AVD_VDMCU_SetClock()
2977             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
2980             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
2983             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
2986             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
2989             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
2992             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
2995             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
2998             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3)|BIT(2), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3001             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3007         RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BIT(1));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3011         RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(1), BIT(1));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3029 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2));  // 20090628 BY put mailbo0 clock sett…  in HAL_AVD_VDMCU_SetClock()
3035             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3)|BIT(2), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3038             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3041             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3044             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3047             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3050             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3053             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3056             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3059             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3065         RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BIT(1));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3069         RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(1), BIT(1));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3484     RIU_WriteRegBit (L_BK_CLKGEN0(0x21), DISABLE, BIT(0)); // CLK_VDMCU, 0:Enable 1:Disable  in HAL_AVD_AFEC_SetClock()
3487     RIU_WriteByteMask (L_BK_CLKGEN0(0x22), 0x00, BMASK(3:0));// CLK_mailbox0  in HAL_AVD_AFEC_SetClock()
3489     RIU_WriteRegBit (L_BK_CLKGEN0(0x23), bEnable, BIT(0));// CLK_VD2X  in HAL_AVD_AFEC_SetClock()
3507         RIU_WriteRegBit(L_BK_CLKGEN0(0x00), DISABLE, BIT(4));  in HAL_AVD_AFEC_SetClockSource()
3530         RIU_WriteRegBit(L_BK_CLKGEN0(0x00), ENABLE, BIT(4));  in HAL_AVD_AFEC_SetClockSource()