Lines Matching refs:L_BK_CLKGEN0
6315 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
6321 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6324 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6327 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6330 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6333 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6336 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6339 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6342 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6345 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6351 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BIT(1)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6355 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(1), BIT(1)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6373 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
6379 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6382 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6385 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6388 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6391 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6394 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6397 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6400 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6403 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6409 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BIT(1)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6413 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(1), BIT(1)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6840 RIU_WriteRegBit (L_BK_CLKGEN0(0x21), DISABLE, BIT(0)); // CLK_VDMCU, 0:Enable 1:Disable in HAL_AVD_AFEC_SetClock()
6843 RIU_WriteByteMask (L_BK_CLKGEN0(0x22), 0x00, BMASK(3:0));// CLK_mailbox0 in HAL_AVD_AFEC_SetClock()
6845 RIU_WriteRegBit (L_BK_CLKGEN0(0x23), bEnable, BIT(0));// CLK_VD2X in HAL_AVD_AFEC_SetClock()
6863 RIU_WriteRegBit(L_BK_CLKGEN0(0x00), DISABLE, BIT(4)); in HAL_AVD_AFEC_SetClockSource()
6886 RIU_WriteRegBit(L_BK_CLKGEN0(0x00), ENABLE, BIT(4)); in HAL_AVD_AFEC_SetClockSource()