2970 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2));  // 20090628 BY put mailbo0 clock sett…  in HAL_AVD_VDMCU_SetClock()
2976             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
2979             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
2982             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
2985             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
2988             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
2991             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
2994             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
2997             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3)|BIT(2), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3000             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3006         RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BIT(1));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3010         RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(1), BIT(1));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3028 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2));  // 20090628 BY put mailbo0 clock sett…  in HAL_AVD_VDMCU_SetClock()
3034             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3)|BIT(2), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3037             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3040             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3043             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3046             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3049             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3052             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3055             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3058             RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3064         RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BIT(1));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3068         RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(1), BIT(1));  //20090611EL  in HAL_AVD_VDMCU_SetClock()
3483     RIU_WriteRegBit (L_BK_CLKGEN0(0x21), DISABLE, BIT(0)); // CLK_VDMCU, 0:Enable 1:Disable  in HAL_AVD_AFEC_SetClock()
3486     RIU_WriteByteMask (L_BK_CLKGEN0(0x22), 0x00, BMASK(3:0));// CLK_mailbox0  in HAL_AVD_AFEC_SetClock()
3488     RIU_WriteRegBit (L_BK_CLKGEN0(0x23), bEnable, BIT(0));// CLK_VD2X  in HAL_AVD_AFEC_SetClock()
3506         RIU_WriteRegBit(L_BK_CLKGEN0(0x00), DISABLE, BIT(4));  in HAL_AVD_AFEC_SetClockSource()
3529         RIU_WriteRegBit(L_BK_CLKGEN0(0x00), ENABLE, BIT(4));  in HAL_AVD_AFEC_SetClockSource()