Lines Matching refs:L_BK_CLKGEN0
6329 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
6335 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6338 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6341 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6344 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6347 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6350 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6353 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6356 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6359 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6365 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BIT(1)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6369 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(1), BIT(1)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6393 …RIU_WriteByteMask(L_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo0 clock sett… in HAL_AVD_VDMCU_SetClock()
6399 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6402 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6405 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6408 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(4), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6411 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6414 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6417 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6420 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6423 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(3)|BIT(2), BMASK(4:2)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6429 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), 0x00, BIT(1)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6433 RIU_WriteByteMask(L_BK_CLKGEN0(0x21), BIT(1), BIT(1)); //20090611EL in HAL_AVD_VDMCU_SetClock()
6908 RIU_WriteRegBit (L_BK_CLKGEN0(0x21), DISABLE, BIT(0)); // CLK_VDMCU, 0:Enable 1:Disable in HAL_AVD_AFEC_SetClock()
6911 RIU_WriteByteMask (L_BK_CLKGEN0(0x22), 0x00, BMASK(3:0));// CLK_mailbox0 in HAL_AVD_AFEC_SetClock()
6913 RIU_WriteRegBit (L_BK_CLKGEN0(0x23), bEnable, BIT(0));// CLK_VD2X in HAL_AVD_AFEC_SetClock()
6931 RIU_WriteRegBit(L_BK_CLKGEN0(0x00), DISABLE, BIT(4)); in HAL_AVD_AFEC_SetClockSource()
6954 RIU_WriteRegBit(L_BK_CLKGEN0(0x00), ENABLE, BIT(4)); in HAL_AVD_AFEC_SetClockSource()