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Searched refs:INT_AEON_PM (Results 1 – 25 of 30) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/mbx/hal/k6/mbx/
H A DhalMBXINT.c343 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
344 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
H A DregMBXINT.h154 #define INT_AEON_PM BIT(0) macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/curry/mbx/
H A DhalMBXINT.c343 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
344 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
H A DregMBXINT.h154 #define INT_AEON_PM BIT(0) macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/k6lite/mbx/
H A DhalMBXINT.c343 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
344 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
H A DregMBXINT.h154 #define INT_AEON_PM BIT(0) macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/kano/mbx/
H A DhalMBXINT.c343 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
344 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
H A DregMBXINT.h154 #define INT_AEON_PM BIT(0) macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/mooney/mbx/
H A DhalMBXINT.c343 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
344 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
H A DregMBXINT.h151 #define INT_AEON_PM BIT(0) macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/maldives/mbx/
H A DhalMBXINT.c341 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
342 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
H A DregMBXINT.h144 #define INT_AEON_PM BIT(0) macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/macan/mbx/
H A DhalMBXINT.c342 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
343 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
/utopia/UTPA2-700.0.x/modules/mbx/hal/messi/mbx/
H A DhalMBXINT.c345 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
346 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
H A DregMBXINT.h151 #define INT_AEON_PM BIT(0) macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/mustang/mbx/
H A DhalMBXINT.c341 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
342 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
H A DregMBXINT.h144 #define INT_AEON_PM BIT(0) macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/mainz/mbx/
H A DhalMBXINT.c345 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
346 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
H A DregMBXINT.h151 #define INT_AEON_PM BIT(0) macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/M7821/mbx/
H A DhalMBXINT.c395 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
396 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
/utopia/UTPA2-700.0.x/modules/mbx/hal/manhattan/mbx/
H A DhalMBXINT.c395 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
396 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
H A DregMBXINT.h176 #define INT_AEON_PM BIT(0) macro
/utopia/UTPA2-700.0.x/modules/mbx/hal/maxim/mbx/
H A DhalMBXINT.c395 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
396 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
/utopia/UTPA2-700.0.x/modules/mbx/hal/maserati/mbx/
H A DhalMBXINT.c395 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
396 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()
/utopia/UTPA2-700.0.x/modules/mbx/hal/M7621/mbx/
H A DhalMBXINT.c395 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM; in MHAL_MBXINT_Fire()
396 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM); in MHAL_MBXINT_Fire()

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