Searched refs:HW4_CFG37_MASK_SCR_PVR1_EN (Results 1 – 12 of 12) sorted by relevance
1836 #define HW4_CFG37_MASK_SCR_PVR1_EN 0x0200 macro
4269 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR1_EN); in HAL_PVR_Skip_Scrmb()4283 REG16_CLR(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR1_EN); in HAL_PVR_Skip_Scrmb()
1874 #define HW4_CFG37_MASK_SCR_PVR1_EN 0x0200 macro
5637 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR1_EN); in HAL_PVR_Skip_Scrmb()5657 REG16_CLR(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR1_EN); in HAL_PVR_Skip_Scrmb()
1876 #define HW4_CFG37_MASK_SCR_PVR1_EN 0x0200 macro
1956 #define HW4_CFG37_MASK_SCR_PVR1_EN 0x0200 macro
1928 #define HW4_CFG37_MASK_SCR_PVR1_EN 0x0200 macro
2005 #define HW4_CFG37_MASK_SCR_PVR1_EN 0x0200 macro
6152 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR1_EN); in HAL_PVR_Skip_Scrmb()6172 REG16_CLR(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR1_EN); in HAL_PVR_Skip_Scrmb()
5781 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR1_EN); in HAL_PVR_Skip_Scrmb()5801 REG16_CLR(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR1_EN); in HAL_PVR_Skip_Scrmb()