Searched refs:HW4_CFG35_BYPASS_TIMESTAMP_SEL1 (Results 1 – 12 of 12) sorted by relevance
1808 #define HW4_CFG35_BYPASS_TIMESTAMP_SEL1 0x0200 macro
4367 REG16_CLR(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL1); in HAL_PVR_PauseTime_En()4381 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL1); in HAL_PVR_PauseTime_En()
1846 #define HW4_CFG35_BYPASS_TIMESTAMP_SEL1 0x0200 macro
5765 REG16_CLR(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL1); in HAL_PVR_PauseTime_En()5785 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL1); in HAL_PVR_PauseTime_En()
1848 #define HW4_CFG35_BYPASS_TIMESTAMP_SEL1 0x0200 macro
1930 #define HW4_CFG35_BYPASS_TIMESTAMP_SEL1 0x0200 macro
1902 #define HW4_CFG35_BYPASS_TIMESTAMP_SEL1 0x0200 macro
1979 #define HW4_CFG35_BYPASS_TIMESTAMP_SEL1 0x0200 macro
6280 REG16_CLR(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL1); in HAL_PVR_PauseTime_En()6300 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL1); in HAL_PVR_PauseTime_En()
5909 REG16_CLR(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL1); in HAL_PVR_PauseTime_En()5929 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL1); in HAL_PVR_PauseTime_En()