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Searched refs:HVD_RIU_WRITE_BYTE (Results 1 – 25 of 31) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maserati/hvd/
H A DregHVD.h125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } macro
141 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg…
147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
154 … HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
155 … HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \
172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \
179 … HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \
181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \
192 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32R…
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/manhattan/hvd/
H A DregHVD.h125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } macro
141 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg…
147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
154 … HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
155 … HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \
172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \
179 … HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \
181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \
192 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32R…
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/macan/hvd/
H A DregHVD.h125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } macro
141 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg…
147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
154 … HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
155 … HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \
172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \
179 … HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \
181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \
192 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32R…
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7821/hvd/
H A DregHVD.h125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } macro
141 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg…
147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
154 … HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
155 … HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \
172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \
179 … HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \
181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \
192 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32R…
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maxim/hvd/
H A DregHVD.h125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } macro
141 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg…
147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
154 … HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
155 … HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \
172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \
179 … HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \
181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \
192 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32R…
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7621/hvd/
H A DregHVD.h125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } macro
141 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg…
147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
154 … HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
155 … HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \
172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \
179 … HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \
181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \
192 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32R…
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mustang/hvd_ex/
H A DregHVD_EX.h125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } macro
141 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg…
147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
154 … HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
155 … HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \
172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \
179 … HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \
181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \
192 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32R…
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maldives/hvd_ex/
H A DregHVD_EX.h125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } macro
141 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg…
147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
154 … HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
155 … HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \
172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \
179 … HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \
181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \
192 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32R…
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7621/hvd_ex/
H A DregHVD_EX.h125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } macro
141 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg…
147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
154 … HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
155 … HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \
172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \
179 … HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \
181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \
192 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32R…
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/messi/hvd_ex/
H A DregHVD_EX.h125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } macro
141 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg…
147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
154 … HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
155 … HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \
172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \
179 … HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \
181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \
192 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32R…
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/manhattan/hvd_ex/
H A DregHVD_EX.h125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } macro
141 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg…
147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
154 … HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
155 … HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \
172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \
179 … HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \
181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \
192 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32R…
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maldives/hvd_v3/
H A DregHVD_EX.h125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } macro
141 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg…
147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
154 … HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
155 … HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \
172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \
179 … HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \
181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \
192 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32R…
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maxim/hvd_ex/
H A DregHVD_EX.h125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } macro
141 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg…
147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
154 … HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
155 … HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \
172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \
179 … HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \
181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \
192 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32R…
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mainz/hvd_ex/
H A DregHVD_EX.h125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } macro
141 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg…
147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
154 … HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
155 … HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \
172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \
179 … HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \
181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \
192 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32R…
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mustang/hvd_v3/
H A DregHVD_EX.h125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } macro
141 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg…
147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
154 … HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
155 … HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \
172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \
179 … HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \
181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \
192 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32R…
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maserati/hvd_ex/
H A DregHVD_EX.h125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } macro
141 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg…
147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
154 … HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
155 … HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \
172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \
179 … HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \
181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \
192 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32R…
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7821/hvd_ex/
H A DregHVD_EX.h125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } macro
141 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg…
147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
154 … HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
155 … HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \
172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \
179 … HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \
181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \
192 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32R…
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/macan/hvd_ex/
H A DregHVD_EX.h125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } macro
141 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg…
147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
154 … HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
155 … HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \
172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \
179 … HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \
181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \
192 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32R…
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/hvd_v3/
H A DregHVD_EX.h125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } macro
141 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg…
147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
154 … HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
155 … HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \
172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \
179 … HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \
181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \
192 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32R…
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/hvd_v3/
H A DregHVD_EX.h125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } macro
141 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg…
147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
154 … HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
155 … HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \
172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \
179 … HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \
181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \
192 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32R…
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/hvd_v3/
H A DregHVD_EX.h125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } macro
141 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg…
147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
154 … HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
155 … HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \
172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \
179 … HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \
181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \
192 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32R…
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/hvd_v3/
H A DregHVD_EX.h125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } macro
141 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg…
147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
154 … HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
155 … HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \
172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \
179 … HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \
181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \
192 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32R…
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/hvd_v3/
H A DregHVD_EX.h125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } macro
141 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg…
147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
154 … HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
155 … HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \
172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \
179 … HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \
181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \
192 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32R…
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/hvd_v3/
H A DregHVD_EX.h125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } macro
141 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg…
147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
154 … HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
155 … HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \
172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \
179 … HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \
181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \
192 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32R…
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/hvd_v3/
H A DregHVD_EX.h125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } macro
141 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg…
147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
154 … HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
155 … HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \
172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \
179 … HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \
181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \
192 …HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32R…

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