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Searched refs:HDMIRX_COMBOPHY0_REG_BASE (Results 1 – 10 of 10) sorted by relevance

/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdmitx/
H A DhalHDMITx.c2010 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4C, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2011 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4B, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2012 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4A, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2013 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_49, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2014 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_09, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2015 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_22, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2016 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_49, 0x1FFF, 0x0C6A); //chan… in MHal_HDMITx_RxBypass_Mode()
2081 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY1_CONFIG_3C, BIT0, 0x0000); in MHal_HDMITx_Disable_RxBypass()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/hdmitx/
H A DhalHDMITx.c2009 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4C, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2010 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4B, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2011 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4A, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2012 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_49, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2013 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_09, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2014 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_22, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2015 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_49, 0x1FFF, 0x0C6A); //chan… in MHal_HDMITx_RxBypass_Mode()
2080 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY1_CONFIG_3C, BIT0, 0x0000); in MHal_HDMITx_Disable_RxBypass()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdmitx/
H A DhalHDMITx.c2095 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4C, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2096 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4B, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2097 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4A, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2098 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_49, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2099 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_09, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2100 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_22, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2101 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_49, 0x1FFF, 0x0C6A); //chan… in MHal_HDMITx_RxBypass_Mode()
2166 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY1_CONFIG_3C, BIT0, 0x0000); in MHal_HDMITx_Disable_RxBypass()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdmitx/
H A DhalHDMITx.c2041 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4C, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2042 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4B, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2043 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4A, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2044 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_49, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2045 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_09, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2046 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_22, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2047 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_49, 0x1FFF, 0x0C6A); //chan… in MHal_HDMITx_RxBypass_Mode()
2112 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY1_CONFIG_3C, BIT0, 0x0000); in MHal_HDMITx_Disable_RxBypass()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdmitx/
H A DhalHDMITx.c2381 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4C, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2382 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4B, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2383 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4A, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2384 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_49, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2385 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_09, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2386 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_22, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2387 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_49, 0x1FFF, 0x0C6A); //chan… in MHal_HDMITx_RxBypass_Mode()
2452 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY1_CONFIG_3C, BIT0, 0x0000); in MHal_HDMITx_Disable_RxBypass()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdmitx/
H A DhalHDMITx.c2496 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4C, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2497 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4B, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2498 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4A, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2499 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_49, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2500 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_09, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2501 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_22, 0xE000, 0xA000); //[13.… in MHal_HDMITx_RxBypass_Mode()
2502 …MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_49, 0x1FFF, 0x0C6A); //chan… in MHal_HDMITx_RxBypass_Mode()
2567 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY1_CONFIG_3C, BIT0, 0x0000); in MHal_HDMITx_Disable_RxBypass()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/hdmitx/include/
H A DregHDMITx.h128 #define HDMIRX_COMBOPHY0_REG_BASE (0x172800U) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdmitx/include/
H A DregHDMITx.h128 #define HDMIRX_COMBOPHY0_REG_BASE (0x172800U) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdmitx/include/
H A DregHDMITx.h128 #define HDMIRX_COMBOPHY0_REG_BASE (0x172800U) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdmitx/include/
H A DregHDMITx.h128 #define HDMIRX_COMBOPHY0_REG_BASE (0x172800U) macro